Semiconductor device and authentication system

Abstract

In order to realize a silicon PUF of lower power consumption, a semiconductor device includes first and second MIS transistors of the same conductive type in off-state coupled in series, as a PUF element. The PUF element outputs a signal of high level or low level depending on the potential of a connection node of the first and the second MIS transistors. Preferably, the MIS transistors are fin-type FETs.

1 - 11 . (canceled) 
     
     
         12 . A semiconductor device comprising:
 a plurality of cell circuits, each of the cell circuits including   first and second MIS transistors of same conductive type, coupled between a power source node and a ground node in series, with each gate and source coupled together,   a logic circuit that receives a potential of a connection node of the first and the second MIS transistors as an input signal, and   a response signal creating circuit that creates a response signal of one or some bits, based on challenge signals of bits and output signals of the logic circuits,   wherein the respective MIS transistors forming the first and the second MIS transistors and the logic circuit are fin-type FETs,   wherein each of the first and the second MIS transistors is a P-type transistor, and   wherein each back gate of the first and the second MIS transistors is coupled to the power source node.   
     
     
         13 . The semiconductor device according to  claim 12 ,
 wherein each of the cell circuits includes   first and second fin wirings each extending in a first direction, formed on an N-type well and arranged in a second direction crossing the first direction,   a first gate wiring extending in the second direction, coupled to the first fin wiring through a gate insulating film,   a second gate wiring extending in the second direction, coupled to the second fin wiring through the gate insulating film,   a first local wiring extending in the second direction, directly coupled to both the first and the second fin wirings,   a second local wiring extending in the second direction, directly coupled to the first fin wiring at a position opposite to the first local wiring with the first gate wiring interposed therebetween and coupled to a power source wiring in an upper layer,   a third local wiring extending in the second direction, directly coupled to the second fin wiring at a position opposite to the first local wiring with the second gate wiring interposed therebetween and coupled to a ground wiring in the upper layer,   a fourth local wiring directly coupled to the first gate wiring and the second local wiring, and   a fifth local wiring directly coupled to the second gate wiring and the first local wiring,   wherein the first fin wiring and the first gate wiring form the first MIS transistor, and   wherein the second fin wiring and the second gate wiring form the second MIS transistor.   
     
     
         14 . The semiconductor device according to  claim 12 ,
 wherein the response signal creating circuit includes a selector circuit that outputs one or some output signals selected from the output signals of the logic circuits as the response signal, according to the challenge signal.   
     
     
         15 . The semiconductor device according to  claim 12 , comprising
 N pieces (N is even number) of the cell circuits,   wherein the response signal creating circuit includes N/2 pieces of selectors each corresponding to the two individual cell circuits, and   wherein each of the selectors outputs an output signal from one of the corresponding two cell circuits as a value of bit corresponding to the response signal, according to a value of the challenge signal of the corresponding bit of the N/2 bits of the challenge signals.   
     
     
         16 . The semiconductor device according to  claim 12 ,
 wherein the logic circuit includes an inverter that inverts a logic level of the input signal.