Sense amplifier for high speed sensing, memory apparatus and system including the same

Abstract

A sense amplifier includes a current supply unit, an amplification unit, a pass transistor and a latch unit. The current supply unit may be configured to provide a sensing current to a sensing node. The amplification unit may be configured to amplify a voltage difference between the read reference voltage with the voltage level of the global bit line. The pass transistor may be configured to transfer a current from the sensing node to the global bit line based on a signal output from the amplification unit. The latch unit may be configured to generate an output signal by detecting a voltage level change of the sensing node.

What is claimed is: 
     
         1 . A sense amplifier comprising:
 a current supply unit configured to provide a sensing current to a sensing node;   an amplification unit configured to amplify a read reference voltage with a voltage level of a global bit line to output a signal;   a pass transistor configured to transfer a current from the sensing node to the global bit line based on the signal output from the amplification unit; and   a latch unit configured to generate an output signal by detecting a voltage level of the sensing node, and to block current supply to the global bit line based on the output signal.   
     
     
         2 . The sense amplifier of  claim 1 , wherein the current supply unit includes a clamping current source, and adjusts an amount of the sensing current by adjusting an amount of a current flowing through the clamping current source. 
     
     
         3 . The sense amplifier of  claim 2 , wherein the current supply unit further includes a precharge switch configured to provide a precharge current to the sensing node based on a precharge signal, and an amount of the precharge current is greater than that of the sensing current. 
     
     
         4 . The sense amplifier of  claim 1 , wherein the latch unit includes a detection portion configured to generate the output signal by detecting the voltage level of the sensing node when a latch enable signal is enabled. 
     
     
         5 . The sense amplifier of  claim 4 , wherein the latch unit further includes a current switch configured to couple the pass transistor to the global bit line based on a sensing enable signal. 
     
     
         6 . The sense amplifier of  claim 5 , wherein the latch unit disables the sensing enable signal based on the output signal, and the current switch de-couples the pass transistor from the global bit line when the sensing enable signal is disabled. 
     
     
         7 . The sense amplifier of  claim 4 , wherein the latch unit further includes a discharge portion configured to discharge the global bit line based on a detection result of the detection portion. 
     
     
         8 . The sense amplifier of  claim 1 , wherein the pass transistor has a gate coupled to an output portion of the amplification unit which outputs the signal, a drain coupled to the sensing node, and a source coupled to the global bit line. 
     
     
         9 . The sense amplifier of  claim 1 , wherein the pass transistor provides a greater amount of current to the global bit line as the voltage level of the global bit line becomes lower, and provides a smaller amount of current to the global bit line as the voltage level of the global bit line becomes higher. 
     
     
         10 . A sense amplifier comprising:
 a current supply unit configured to provide a sensing current to a sensing node;   a first current clamping unit configured to adjust an amount of the sensing current based on a read reference voltage;   an amplification unit configured to amplify the read reference voltage with a voltage level of the global bit line to output a signal;   a second current clamping unit configured to adjust an amount of a current provided to the global bit line based on the voltage level of the global bit line;   a pass transistor configured to couple the sensing node to the global bit line based on the signal output from the amplification unit; and   a latch unit configured to generate an output signal by detecting a voltage level of the sensing node.   
     
     
         11 . The sense amplifier of  claim 10 , wherein the current supply unit further includes a precharge switch configured to provide a precharge current to the sensing node based on a precharge signal, and an amount of the precharge current is greater than that of the sensing current. 
     
     
         12 . The sense amplifier of  claim 10 , wherein the pass transistor has a gate coupled to an output portion of the amplification unit which outputs the signal, a drain coupled to the sensing node, and a source coupled to the global bit line. 
     
     
         13 . The sense amplifier of  claim 10 , wherein the latch unit includes a detection portion configured to generate the output signal by detecting the voltage level of the sensing node when a latch enable signal is enabled. 
     
     
         14 . The sense amplifier of  claim 13 , wherein the latch unit further includes a current switch configured to couple the pass transistor to the global bit line based on a sensing enable signal. 
     
     
         15 . The sense amplifier of  claim 14 , wherein the latch unit disables the sensing enable signal based on the output signal, and the current switch de-couples the pass transistor from the global bit line when the sensing enable signal is disabled. 
     
     
         16 . The sense amplifier of  claim 13 , wherein the latch unit further includes a discharge portion configured to discharge the global bit line based on a detection result of the detection portion. 
     
     
         17 . A memory apparatus comprising:
 a sense amplifier comprising:   a current supply unit configured to provide a sensing current to a sensing node;   an amplification unit configured to amplify a read reference voltage with a voltage level of a global bit line to output a signal;   a pass transistor configured to transfer a current from the sensing node to the global bit line based on the signal output from the amplification unit; and   a latch unit configured to generate an output signal by detecting a voltage level of the sensing node, and to block current supply to the global bit line based on the output signal;   a column switch coupled to the sense amplifier through the global bit line; and   a memory cell coupled to the column switch through a bit line.   
     
     
         18 . The memory apparatus of  claim 17 , wherein the column switch is configured to couple the global bit line to the bit line and the memory cell coupled to the bit line based on a column selection signal. 
     
     
         19 . The memory apparatus of  claim 17 ,
 wherein the pass transistor provides a smaller amount of current to the global bit line when the memory cell has a low resistance status or the memory cell has stored a set data, and   wherein the pass transistor provides a greater amount of current to the global bit line when the memory cell has a high resistance status and/or the memory cell has stored a reset data.