Semiconductor device

Abstract

A semiconductor device including a bus master that receives a clock; a first bus slave that receives a first slave clock and has a first number of waits, and a second bus slave that receives a second slave clock and has a second number of waits, wherein the second number of waits is higher than the first number of waits, and wherein a phase difference between the clock and the first slave clock is higher than a phase difference between the clock and the second slave clock.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a bus master that receives a clock;   a first bus slave that receives a first slave clock and has a first number of waits; and   a second bus slave that receives a second slave clock and has a second number of waits,   wherein the second number of waits is higher than the first number of waits, and   wherein a phase difference between the clock and the first slave clock is greater than a phase difference between the clock and the second slave clock.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising:
 a delay circuit that generates the phase difference between the clock and the first slave clock.   
     
     
         3 . The semiconductor device according to  claim 2 , further comprising:
 a clock generator,   wherein the delay circuit is disposed between the clock generator and the first bus slave.   
     
     
         4 . The semiconductor device according to  claim 2 , further comprising:
 a clock generator,   wherein the delay circuit is disposed between the clock generator and the bus master.   
     
     
         5 . The semiconductor device according to  claim 1 , wherein the bus master is one of a central processing unit (CPU) and a direct memory access (DMA) controller. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the first bus slave comprises a memory.