Power management for pci express

Abstract

Systems and methods are provided for managing power of a device coupled with a transceiver module, in communication with a high-speed interface. In one aspect, a dynamic clock trunk tree associated with the transceiver module is controlled by a trunk driver having a first clock tree gate. A dynamic clock leaf tree associated with the device is controlled by a leaf driver having a second clock tree gate. Significant power savings may be achieved, for example, by triggering activation of clock gating mechanisms.

What is claimed is: 
     
         1 . A method for dynamic clock gating in an electrical device comprising:
 upon detecting that a high speed serial interface (HSSI) link of the electrical device entered a low power state, gating a clock signal in a first clock tree of a first component of the electrical device, wherein a first component is coupled to the HSSI link through a transceiver coupled to the HSSI link, wherein the clock signal is generated in a clock signal generator of the transceiver;   upon an absence of a wake signal from the first component link or from the transceiver within a timeout window, shutting down the clock signal generator that generates the clock signal;   upon receiving the wake signal from the first component or from the transceiver, turning on the clock signal generator; and   upon receiving the wake signal from one of the first component or from the transceiver, ungating the first clock tree.