US2018213230A1PendingUtilityA1

Video encoder and method of operating the same

Assignee: RENESAS ELECTRONICS CORPPriority: Oct 2, 2013Filed: Mar 23, 2018Published: Jul 26, 2018
Est. expiryOct 2, 2033(~7.2 yrs left)· nominal 20-yr term from priority
H04N 19/593H04N 19/176H04N 19/124H04N 19/146H04N 19/152H04N 19/126H04N 19/115H04N 19/50H04N 19/149
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Claims

Abstract

The present invention provides a video encoder and a method of operating the video encoder to implement high-precision bit rate control by reducing the risk of overflow of an intermediate buffer coupled between a quantizer and an encoding section. The intermediate buffer supplies a selection control signal indicative of whether the amount of stored data is large or small to a selector. If the selection control signal indicates large, the selector outputs an estimated code amount from a code amount estimation section to the rate controller. If the selection control signal indicates small, the selector outputs an actual code amount from the encoding section to the rate controller. The rate controller calculates the quantization scale according to the output of the selector and feedbacks the calculated quantization scale to the quantizer. The quantizer adjusts the quantizer scale.

Claims

exact text as granted — not AI-modified
1 - 20 . (canceled) 
     
     
         21 . A video encoder comprising:
 a frequency converter;   a quantizer;   an encoding section;   an intermediate buffer;   a code amount estimation section;   a code amount selector; and   a rate controller,   wherein the frequency converter performs a frequency conversion process on an input signal,   wherein the quantizer performs a quantization process on the result of the frequency conversion process performed by the frequency converter,   wherein the encoding section generates a compressed video bit stream by performing an encoding process on the result of the quantization process performed by the quantizer,   wherein the intermediate buffer is coupled between the output terminal of the quantizer and the input terminal of the encoding section in order to absorb a difference between a processing speed of the quantizer and a processing speed of the encoding section,   wherein the input terminal of the code amount estimation section is coupled to the output terminal of the quantizer,   wherein an estimated code amount generated from the output terminal of the code amount estimation section is supplied to the first input terminal of the code amount selector,   wherein an actual code amount of the compressed video bit stream encoded by the encoding section is supplied to the second input terminal of the code amount selector,   wherein a determination signal indicative of whether the amount of data stored in the intermediate buffer is large or small is supplied to a selection control terminal of the code amount selector,   wherein the output terminal of the code amount selector is coupled to the input terminal of the rate controller,   wherein an output signal of the rate controller is used to adjust a quantization scale of the quantizer,   wherein, if the determination signal indicates that the amount of data stored in the intermediate buffer is large, the estimated code amount from the code amount estimation section, which is supplied to the first input terminal of the code amount selector, is output to the output terminal of the code amount selector, and the estimated code amount is used to adjust the quantization scale of the quantizer, and   wherein, if the determination signal indicates that the amount of data stored in the intermediate buffer is small, the actual code amount from the encoding section, which is supplied to the second input terminal of the code amount selector, is output to the output terminal of the code amount selector, and the actual code amount is used to adjust the quantization scale of the quantizer.   
     
     
         22 . The video encoder according to  claim 21 ,
 wherein the encoding section performs an encoding process by using at least either one of an arithmetic coding method and a variable-length coding method.   
     
     
         23 . The video encoder according to  claim 22 ,
 wherein, when the encoding section performs an encoding process by using the arithmetic coding method, the intermediate buffer absorbs the processing speed difference between the quantization process of the quantizer and the encoding process of the encoding section, which is based on the arithmetic coding method, and   wherein, when the encoding section performs an encoding process by using the variable-length coding method, the intermediate buffer absorbs the processing speed difference between the quantization process of the quantizer and the encoding process of the encoding section, which is based on the variable-length coding method.   
     
     
         24 . The video encoder according to  claim 21 ,
 wherein whether the amount of data stored in the intermediate buffer is large or small is determined by checking whether the amount of stored data is larger than a predetermined threshold or by checking whether the amount of stored data is smaller than the predetermined threshold.   
     
     
         25 . The video encoder according to  claim 22 ,
 wherein the encoding section includes an exponential-Golomb coding section, a variable-length coding processor, and an arithmetic coding processor,   wherein the exponential-Golomb coding section generates an exponential-Golomb code by encoding a syntax element to be encoded, the exponential-Golomb code including a prefix, a separator, and a suffix,   wherein the variable-length coding processor performs a zigzag scan to convert the result of the frequency conversion process performed by the frequency converter, which is quantized by the quantizer, into a one-dimensional vector, and then performs the encoding process based on the variable-length coding method,   wherein the arithmetic coding processor includes a binarizer, a binary arithmetic coding section, and a context calculator,   wherein the binarizer generates a binary signal from a multivalued input signal, and the generated binary signal is encoded into an encoded bit stream by the binary arithmetic coding section,   wherein the context calculator dynamically calculates and updates an event probability model for the binary signal in accordance with the condition of a neighboring symbol, the event probability model being an encoding target symbol, and   wherein the binary arithmetic coding section encodes the binary signal into an encoded bit stream in accordance with the event probability model calculated and updated by the context calculator.   
     
     
         26 . The video encoder according to  claim 25 ,
 wherein the intermediate buffer is disposed in the arithmetic coding processor and coupled between the binarizer and the binary arithmetic coding section.   
     
     
         27 . The video encoder according to  claim 26 ,
 wherein an actual code amount of the binary arithmetic coding section in the arithmetic coding processor is supplied to the second input terminal of the code amount selector.   
     
     
         28 . The video encoder according to  claim 21 , further comprising:
 a motion vector detector, a motion compensator, a subtractor, an inverse quantizer, an inverse frequency converter, a memory, an intra-prediction section, and a prediction selector,   wherein the motion vector detector generates a motion vector from a video signal to be encoded and from a reference image stored in the memory,   wherein the motion compensator generates a motion-compensated prediction signal in response to the motion vector generated from the motion vector detector and to the reference signal stored in the memory,   wherein the video signal is supplied to one input terminal of the subtractor, the motion-compensated prediction signal generated from the motion compensator is supplied to the other input terminal of the subtractor, and a predictive residual is generated from the output terminal of the subtractor,   wherein the predictive residual generated from the output terminal of the subtractor is supplied to the input terminal of the frequency converter as the input signal for the frequency conversion process,   wherein the inverse quantizer and the inverse frequency converter perform a local decoding process on the result of the quantization process performed by the quantizer, and the result of the local decoding process is stored in the memory as the reference image,   wherein the result of the local decoding process performed by the inverse quantizer and the inverse frequency converter is stored in the memory as an intra-reference image,   wherein the video signal is supplied to one input terminal of the intra-prediction section, and the intra-reference image stored in the memory is supplied to the other input terminal of the intra-prediction section so that the intra-prediction section generates an intra-prediction signal about the video signal supplied to the one input terminal, and   wherein the prediction selector selects either one of the motion-compensated prediction signal generated from the motion compensator and the intra-prediction signal generated from the intra-prediction section and supplies the selected prediction signal to the other input terminal of the subtractor.   
     
     
         29 . The video encoder according to  claim 21 ,
 wherein the frequency converter, the quantizer, the encoding section, the intermediate buffer, the code amount estimation section, the code amount selector, and the rate controller are integrated into a single semiconductor chip in a semiconductor integrated circuit.   
     
     
         30 . The video encoder according to  claim 28 ,
 wherein the motion vector detector, the motion compensator, the subtractor, the inverse quantizer, the inverse frequency converter, the encoding section, the intra-prediction section, and the prediction selector are further integrated into the single semiconductor chip in the semiconductor integrated circuit.   
     
     
         31 . The video encoder according to  claim 21 ,
 wherein the compressed video bit stream is generated by encoding the video signal in compliance with the H.264 standard or the H.265 standard, whichever is arbitrarily selected.   
     
     
         32 . A method of operating a video encoder having a frequency converter, a quantizer, an encoding section, an intermediate buffer, a code amount estimation section, a code amount selector, and a rate controller, the method comprising the steps of:
 causing the frequency converter to perform a frequency conversion process on an input signal;   causing the quantizer to perform a quantization process on the result of the frequency conversion process performed by the frequency converter;   causing the encoding section to generate a compressed video bit stream by allowing the encoding section to perform an encoding process on the result of the quantization process performed by the quantizer;   coupling the intermediate buffer between the output terminal of the quantizer and the input terminal of the encoding section in order to absorb a difference between a processing speed of the quantizer and a processing speed of the encoding section;   coupling the input terminal of the code amount estimation section to the output terminal of the quantizer;   causing an estimated code amount, which is generated from the output terminal of the code amount estimation section, to be supplied to a first input terminal of the code amount selector;   causing an actual code amount of the compressed video bit stream, which is encoded by the encoding section, to be supplied to a second input terminal of the code amount selector;   causing a determination signal indicative of whether the amount of data stored in the intermediate buffer is large or small to be supplied to a selection control terminal of the code amount selector;   coupling the output terminal of the code amount selector to the input terminal of the rate controller, an output signal of the rate controller being used to adjust the quantization scale of the quantizer;   if the determination signal indicates that the amount of data stored in the intermediate buffer is large, causing the estimated code amount from the code amount estimation section, which is supplied to the first input terminal of the code amount selector, to be output to the output terminal of the code amount selector, the estimated code amount then being used to adjust the quantization scale of the quantizer; and   if the determination signal indicates that the amount of data stored in the intermediate buffer is small, causing the actual code amount from the encoding section, which is supplied to the second input terminal of the code amount selector, to be output to the output terminal of the code amount selector, the actual code amount then being used to adjust the quantization scale of the quantizer.   
     
     
         33 . The method according to  claim 32 ,
 wherein the encoding section performs an encoding process based on either one of an arithmetic coding method and a variable-length coding method.   
     
     
         34 . The method according to  claim 33 ,
 wherein, when the encoding section performs an encoding process based on the arithmetic coding method, the intermediate buffer absorbs the processing speed difference between the quantization process of the quantizer and the encoding process of the encoding section, which is based on the arithmetic coding method, and   wherein, when the encoding section performs an encoding process based on the variable-length coding method, the intermediate buffer absorbs the processing speed difference between the quantization process of the quantizer and the encoding process of the encoding section, which is based on the variable-length coding method.   
     
     
         35 . The method according to  claim 32 ,
 wherein whether the amount of data stored in the intermediate buffer is large or small is determined by checking whether the amount of stored data is larger than a predetermined threshold or by checking whether the amount of stored data is smaller than the predetermined threshold.   
     
     
         36 . The method according to  claim 33 ,
 wherein the encoding section includes an exponential-Golomb coding section, a variable-length coding processor, and an arithmetic coding processor,   wherein the exponential-Golomb coding section generates an exponential-Golomb code by encoding a syntax element to be encoded, the exponential-Golomb code including a prefix, a separator, and a suffix,   wherein the variable-length coding processor performs a zigzag scan to convert the result of the frequency conversion process performed by the frequency converter, which is quantized by the quantizer, into a one-dimensional vector, and then performs the encoding process based on the variable-length coding method,   wherein the arithmetic coding processor includes a binarizer, a binary arithmetic coding section, and a context calculator,   wherein the binarizer generates a binary signal from a multivalued input signal, the generated binary signal being encoded into an encoded bit stream by the binary arithmetic coding section,   wherein the context calculator dynamically calculates and updates an event probability model for the binary signal in accordance with the condition of a neighboring symbol, the event probability model being an encoding target symbol, and   wherein the binary arithmetic coding section encodes the binary signal into an encoded bit stream in accordance with the event probability model calculated and updated by the context calculator.   
     
     
         37 . The method according to  claim 36 ,
 wherein the intermediate buffer is disposed in the arithmetic coding processor and coupled between the binarizer and the binary arithmetic coding section.

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