Embedded stacked die packages and related methods

Abstract

Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a first semiconductor die at least partially encapsulated in a first mold layer;   a first redistribution layer (RDL) coupled with the first mold layer, the first redistribution layer electrically coupled with the first semiconductor die;   a second semiconductor die coupled with the first redistribution layer;   the second semiconductor die and the first redistribution layer at least partially encapsulated in a second mold layer; and   a second redistribution layer (RDL) coupled with the second mold layer, the second redistribution layer electrically coupled with the second semiconductor die and the second redistribution layer at least partially encapsulated in a third mold layer.   
     
     
         2 . The package of  claim 1 , wherein the first redistribution layer is coupled with one or more of a plurality of electrically conductive elements. 
     
     
         3 . The package of  claim 1 , wherein the first mold layer, the second mold layer, and the third mold layer are formed using compression molding. 
     
     
         4 . The package of  claim 1 , further comprising a third semiconductor die coupled at least partially encapsulated in the first mold layer. 
     
     
         5 . The package of  claim 1 , wherein the package does not comprise a sequential build-up (SBU) laminate substrate. 
     
     
         6 . The package of  claim 1 , wherein the package comprises no bondwires and no electrically conductive clips. 
     
     
         7 . The package of  claim 1 , wherein the first redistribution layer is electrically coupled with the first semiconductor die through one or more electrically conductive pillars, the second redistribution layer is electrically coupled with the second semiconductor die through one or more electrically conductive pillars, and the second redistribution layer is electrically coupled with the first redistribution layer through one or more electrically conductive pillars. 
     
     
         8 . The package of  claim 1 , further comprising a heat dissipation device coupled with the second redistribution layer, the heat dissipation device at least partially encapsulated in the third mold layer, wherein a portion of the heat dissipation device is exposed on an outer surface of the package through an opening in the third mold layer. 
     
     
         9 . A semiconductor package, comprising:
 a first semiconductor die at least partially encapsulated in a first mold layer;   one or more first vias through the first mold layer at least partially filled with an electrically conductive material to form one or more first pillars;   a first redistribution layer (RDL) coupled with the first mold layer, the first redistribution layer electrically coupled with the first semiconductor die through the one or more first pillars;   a second semiconductor die coupled with the first redistribution layer;   the second semiconductor die and the first redistribution layer at least partially encapsulated in a second mold layer;   one or more second vias through the second mold layer at least partially filled with an electrically conductive material to form one or more second pillars; and   a second redistribution layer (RDL) coupled with the second mold layer, the second redistribution layer electrically coupled with the second semiconductor die through the one or more second pillars.   
     
     
         10 . The method of  claim 9 , further comprising electrically coupling the first redistribution layer with one or more of a plurality of electrically conductive elements. 
     
     
         11 . The package of  claim 9 , wherein the first mold layer, the second mold layer, and the third mold layer are formed using compression molding. 
     
     
         12 . The package of  claim 9 , further comprising a third semiconductor die coupled at least partially encapsulated in the first mold layer. 
     
     
         13 . The package of  claim 9 , wherein the package does not comprise a sequential build-up (SBU) laminate substrate. 
     
     
         14 . The package of  claim 9 , wherein the package comprises no bondwires and no electrically conductive clips. 
     
     
         15 . The package of  claim 9 , wherein the second redistribution layer is electrically coupled with the first redistribution layer through the one or more second pillars. 
     
     
         16 . The package of  claim 9 , further comprising a heat dissipation device coupled with the second redistribution layer, the heat dissipation device at least partially encapsulated in the third mold layer, wherein a portion of the heat dissipation device is exposed on an outer surface of the package through an opening in the third mold layer. 
     
     
         17 . A semiconductor package, comprising:
 a first semiconductor die coupled with a third semiconductor die, the first semiconductor die and the third semiconductor die at least partially encapsulated in a first mold layer;   a first redistribution layer (RDL) coupled with the first mold layer, the first redistribution layer electrically coupled with the first semiconductor die;   a second semiconductor die coupled with the first redistribution layer;   the second semiconductor die and the first redistribution layer at least partially encapsulated in a second mold layer; and   a second redistribution layer (RDL) coupled with the second mold layer, the second redistribution layer electrically coupled with the second semiconductor die and the second redistribution layer at least partially encapsulated in a third mold layer.   
     
     
         18 . The package of  claim 17 , wherein the first redistribution layer is electrically coupled with one or more of a plurality of electrically conductive elements. 
     
     
         19 . The package of  claim 17 , wherein the stacked embedded package comprises no sequential build-up (SBU) laminate substrates, no bondwires, and no electrically conductive clips. 
     
     
         20 . The method of  claim 17 , further comprising a heat dissipation device coupled with the second redistribution layer.