US2018203807A1PendingUtilityA1

Partitioning tlb or cache allocation

Assignee: ADVANCED RISC MACH LTDPriority: Jan 13, 2017Filed: Jan 13, 2017Published: Jul 19, 2018
Est. expiryJan 13, 2037(~10.5 yrs left)· nominal 20-yr term from priority
G06F 12/084G06F 2212/1048G06F 12/109G06F 12/126G06F 12/0842G06F 2212/6042G06F 2212/601G06F 2212/6046G06F 12/1036G06F 2212/684G06F 2212/1041G06F 12/1027G06F 12/0891G06F 12/1045G06F 12/12G06F 2212/452G06F 2212/68G06F 12/0875
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Claims

Abstract

A request for data from a cache (TLB or data/instruction cache) specifies a partition identifier allocated to a software execution environment associated with the request. Allocation of data to the cache is controlled based on a set of configuration information selected based on the partition identifier specified by the request. For a TLB, this allows different allocation policies to be used for requests associated with different software execution environments. In one example, the cache allocation is controlled based on an allocation threshold specified by the selected set of configuration information, which limits the maximum number of cache entries allowed to be allocated with data associated with the corresponding partition identifier.

Claims

exact text as granted — not AI-modified
I claim: 
     
         1 . An apparatus comprising:
 processing circuitry to perform data processing in response to instructions of one of a plurality of software execution environments; and   a memory management unit to perform memory address translation, the memory management unit comprising an address translation cache to store address translation data;   wherein in response to an address translation cache miss detected for an address translation request specifying a partition identifier allocated to a software execution environment associated with the address translation request, the memory management unit is configured to control allocation of address translation data to the address translation cache in dependence on one of a plurality of sets of configuration information selected in dependence on the partition identifier specified by the address translation request.   
     
     
         2 . The apparatus according to  claim 1 , wherein in response to the address translation request, the memory management unit is configured to perform a lookup of the address translation cache which is independent of the partition identifier specified by the address translation request. 
     
     
         3 . The apparatus according to  claim 1 , wherein the address translation cache comprises a translation lookaside buffer comprising at least one entry to store address translation mapping information specifying a mapping between a first address and a second address. 
     
     
         4 . The apparatus according to  claim 1 , wherein the address translation cache comprises a page walk cache comprising at least one entry to store a page table entry or an address of a page table entry. 
     
     
         5 . The apparatus according to  claim 1 , wherein in response to the address translation cache miss, the memory management unit is configured to control allocation of address translation data to the address translation cache in dependence on a cache portion map specified by the selected set of configuration information, the cache portion map identifying which portions of the address translation cache are allowed to be allocated with address translation data in response to the address translation request. 
     
     
         6 . The apparatus according to  claim 1 , wherein in response to the address translation cache miss, the memory management unit is configured to control allocation of data to the address translation cache in dependence on an allocation threshold specified by the selected set of configuration information, the allocation threshold identifying a maximum number of entries of the address translation cache allowed to be allocated with address translation data associated with the corresponding partition identifier. 
     
     
         7 . An apparatus comprising:
 processing circuitry to perform data processing in response to instructions of one of a plurality of software execution environments; and   a cache comprising a plurality of entries to store data;   wherein in response to a cache miss detected for a cache access request specifying a partition identifier allocated to a software execution environment associated with the cache access request, the cache is configured to control allocation of data to the cache in dependence on one of a plurality of sets of configuration information selected in dependence on the partition identifier specified by the cache access request;   wherein in a first cache control mode, the cache is configured to control allocation of data to the cache in dependence on a threshold specified by the selected set of configuration information, the threshold identifying a maximum number of entries of the cache allowed to be allocated with data associated with the corresponding partition identifier.   
     
     
         8 . The apparatus according to  claim 7 , wherein in response to the cache access request, the cache is configured to perform a cache lookup which is independent of the partition identifier specified by the cache access request. 
     
     
         9 . The apparatus according to  claim 7 , wherein each valid entry of the cache is associated with a partition identifier tag identifying a partition identifier of the cache access request which caused the corresponding data to be allocated to that entry. 
     
     
         10 . The apparatus according to  claim 9 , wherein on writing back data from a given entry of the cache to another cache or memory, the cache is configured to issue a memory transaction specifying the partition identifier identified by the partition identifier tag of said given entry. 
     
     
         11 . The apparatus according to  claim 7 , comprising a plurality of allocation counters, each allocation counter to count a number of entries of the cache allocated for data associated with a given partition identifier. 
     
     
         12 . The apparatus according to  claim 7 , wherein in the first cache control mode, the cache is configured to prevent data being allocated to the cache in response to the cache miss if the number of entries allocated for data associated with the partition identifier specified by the cache access request is equal to or exceeds the maximum number indicated by said threshold. 
     
     
         13 . The apparatus according to  claim 7 , wherein in the first cache control mode, the cache is configured to allocate data to the cache in response to the cache miss and invalidate, evict or replace other cached data associated with the partition identifier specified by the cache access request if the number of entries allocated for data associated with the partition identifier specified by the cache access request is equal to or exceeds the maximum number indicated by said threshold. 
     
     
         14 . The apparatus according to  claim 7 , wherein the threshold identifies the maximum number of entries as a fraction of the capacity of the cache. 
     
     
         15 . The apparatus according to  claim 7 , wherein in a second cache control mode, the cache is configured to control allocation of data to the cache in dependence on a cache portion map specified by the selected set of configuration information, the cache portion map identifying which portions of the cache are allowed to be allocated with data in response to the cache access request. 
     
     
         16 . The apparatus according to  claim 15 , wherein the cache is configured to select whether to use the first cache control mode or the second cache control mode in dependence on a configuration value specified in a control register. 
     
     
         17 . The apparatus according to  claim 7 , wherein the cache comprises one of:
 a data cache;   an instruction cache;   a translation lookaside buffer; and   a page walk cache.   
     
     
         18 . A method comprising:
 performing data processing in response to instructions of one of a plurality of software execution environments;   performing memory address translation using an address translation cache storing address translation data; and   in response to an address translation cache miss detected for an address translation request specifying a partition identifier allocated to a software execution environment associated with the address translation request, controlling allocation of address translation data to the address translation cache in dependence on one of a plurality of sets of configuration information selected in dependence on the partition identifier specified by the address translation request.   
     
     
         19 . A method comprising:
 performing data processing in response to instructions of one of a plurality of software execution environments;   accessing data in a cache comprising a plurality of entries; and   in response to a cache miss detected for a cache access request specifying a partition identifier allocated to a software execution environment associated with the cache access request, controlling allocation of data to the cache in dependence on one of a plurality of sets of configuration information selected in dependence on the partition identifier specified by the cache access request;   wherein in a first cache control mode, the allocation of data to the cache is controlled in dependence on a threshold specified by the selected set of configuration information, the threshold identifying a maximum number of entries of the cache allowed to be allocated with data associated with the corresponding partition identifier.

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