US2018198372A1PendingUtilityA1
Galvanically isolated dc-dc converter with bidirectional data transmission
Est. expiryJun 10, 2036(~9.9 yrs left)· nominal 20-yr term from priority
Inventors:Egidio RagoneseNunzio SpinaPierpaolo LombardoNunzio GrecoAlessandro ParisiGiuseppe Palmisano
H10W 90/753H02M 3/33553H02M 3/33523H02M 3/33592H02M 3/33584H02M 1/0012Y02B70/10
48
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Claims
Abstract
A galvanic isolation is provided between a first circuit and a second circuit. A first galvanically isolated link is configured to transfer power from a first circuit to a second circuit across the galvanic isolation. A second galvanically isolated link is configured to feed back an error signal from the second circuit to the first circuit across the galvanic isolation for use in regulating the power transfer and further configured to support bidirectional data communication between the first and second circuits across the galvanic isolation.
Claims
exact text as granted — not AI-modified1 . A galvanic isolation system, comprising:
a first galvanically isolated link configured to transfer power from a first circuit to a second circuit across a galvanic barrier; and a second galvanically isolated link comprising a first transformer, wherein the first transformer is configured to feed back an error signal from the second circuit to the first circuit across the galvanic barrier for use in regulating the power transfer and wherein the first transformer is further configured to pass a bidirectional data communication signal between the first and second circuits across the galvanic barrier.
2 . The system of claim 1 , wherein the first galvanically isolated link comprises:
a first oscillator of the first circuit; and a second transformer having a primary winding coupled to outputs of the first oscillator and a secondary winding coupled to the second circuit.
3 . The system of claim 2 , wherein the second circuit comprises a rectifier circuit coupled to the secondary winding of the second transformer and configured to convert the power transfer to a DC output voltage.
4 . The system of claim 3 , wherein the second circuit further comprises an error amplifier configured to determine a difference between the DC output voltage and a reference voltage and generate said error signal in response thereto.
5 . The system of claim 4 , wherein said second galvanically isolated link comprises:
a second oscillator of the second circuit configured for operation responsive to said error signal; wherein said first transformer has a primary winding coupled to outputs of the second oscillator and a secondary winding coupled to the first circuit.
6 . The system of claim 5 , wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator.
7 . The system of claim 6 , wherein the first circuit comprises:
a detector circuit coupled to the secondary winding of the first transformer and configured to detect said peak amplitude and to generate a control signal; and a control circuit responsive to said control signal and configured to control the first oscillator to regulate power transfer from the first circuit to the second circuit across the galvanic barrier.
8 . The system of claim 7 , wherein the control circuit comprises a pulse width modulation (PWM) control circuit responsive to said control signal and configured to generate a PWM switching signal for controlling on and off actuation of the first oscillator.
9 . The system of claim 5 , wherein the first circuit comprises:
a detector circuit coupled to the secondary winding of the first transformer and configured to detect said error signal and generate a control signal; and a control circuit responsive to said control signal and configured to control the first oscillator to regulate power transfer from the first circuit to the second circuit across the galvanic barrier.
10 . The system of claim 9 , wherein the control circuit comprises a pulse width modulation (PWM) control circuit responsive to said control signal and configured to generate a PWM switching signal for controlling on and off actuation of the first oscillator.
11 . The system of claim 5 , further comprising:
a data modulator circuit having outputs coupled to the primary winding of the first transformer, wherein said data modulator modulates data onto a signal of said bidirectional data communications signal at the primary winding of the first transformer for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the secondary winding of the first transformer, wherein said data demodulator demodulates the data from said signal at the secondary winding of the first transformer.
12 . The system of claim 11 , wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator at the primary winding of the first transformer.
13 . The system of claim 5 , further comprising:
a data modulator circuit having outputs coupled to the secondary winding of the first transformer, wherein said data modulator modulates data onto a signal of said bidirectional data communications signal at the secondary winding of the first transformer for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the primary winding of the first transformer, wherein said data demodulator demodulates the data from said signal at the primary winding of the first transformer.
14 . The system of claim 13 , wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator at the primary winding of the first transformer.
15 . The system of claim 2 , wherein said second galvanically isolated link comprises:
a second oscillator of the second circuit configured for operation responsive to said error signal; wherein said first transformer has a primary winding coupled to outputs of the second oscillator and a secondary winding coupled to the first circuit.
16 . The system of claim 15 , wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator.
17 . The system of claim 15 , wherein the first circuit comprises:
a detector circuit coupled to the secondary winding of the first transformer and configured to detect said error signal and generate a control signal; and a control circuit responsive to said control signal and configured to control the first oscillator to regulate power transfer from the first circuit to the second circuit across the galvanic barrier.
18 . The system of claim 17 , wherein the control circuit comprises a pulse width modulation (PWM) control circuit responsive to said control signal and configured to generate a PWM switching signal for controlling on and off actuation of the first oscillator.
19 . The system of claim 15 , further comprising:
a data modulator circuit having outputs coupled to the primary winding of the first transformer, wherein said data modulator modulates data onto a signal of said bidirectional data communications signal at the primary winding of the first transformer for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the secondary winding of the first transformer, wherein said data demodulator demodulates the data from said signal at the secondary winding of the first transformer.
20 . The system of claim 19 , wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator at the primary winding of the first transformer.
21 . The system of claim 15 , further comprising:
a data modulator circuit having outputs coupled to the secondary winding of the first transformer, wherein said data modulator modulates data onto a signal of said bidirectional data communications signal at the secondary winding of the first transformer for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the primary winding of the first second transformer, wherein said data demodulator demodulates the data from said signal at the primary winding of the first transformer.
22 . The system of claim 21 , wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator at the primary winding of the first transformer.
23 . The system of claim 1 , wherein said first galvanically isolated link comprises a power very high frequency (VHF) oscillator circuit and said second galvanically isolated link comprises a radio frequency (RF) oscillator circuit.
24 . The system of claim 23 , wherein the first circuit comprises a first control circuit configured to control on and off actuation of the power VHF oscillator circuit in response to the error signal, and wherein the second circuit comprises a second control circuit configured to control a peak amplitude of the RF oscillator circuit to communicate the error signal across the galvanic barrier.
25 . The system of claim 24 , further comprising:
a data modulator circuit having outputs coupled to the RF oscillator circuit on a second circuit side of the galvanic barrier, wherein said data modulator modulates data onto a signal of said bidirectional data communications signal at the second circuit side for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the RF oscillator circuit on a first circuit side of the galvanic barrier, wherein said data demodulator demodulates the data from said signal at the first circuit side.
26 . The system of claim 24 , further comprising:
a data modulator circuit having outputs coupled to the RF oscillator circuit on a first circuit side of the galvanic barrier, wherein said data modulator modulates data onto a signal of said bidirectional data communications signal at the first circuit side for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the RF oscillator circuit on a second circuit side of the galvanic barrier, wherein said data demodulator demodulates the data from said signal at the second circuit side.
27 . The system of claim 1 , wherein the first circuit and the first and second transformers are provided on a first integrated circuit chip and the second circuit is provided on a second integrated circuit chip, and further including bonding wires configured for electrically connecting the first and second integrated circuit chips.Join the waitlist — get patent alerts
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