Apparatus and Methods for Testing Semiconductor Devices

Abstract

The invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (FOUP), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site. Each test site contains a wafer probe card assembly and a floating chuck. In use, wafers are loaded from a front opening FOUP into a wafer buffer FOUP from which wafers are retrieved by the wafer handling and alignment assembly. The robot positions the wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly in front of and inside a given test site and aligns the wafer to be tested with the probe card inside the test site using the floating chuck.

What is claimed is: 
     
         1 . A device for testing multiple wafers in parallel, comprising:
 an array of wafer test sites for performing at least one test on a wafer within any one of said wafer test sites;   a mobile wafer handling and alignment carriage for facilitating movement of the wafer into and from any one of said wafer test sites;   a Cartesian robot for placing said mobile wafer handling and alignment carriage inside any one of said wafer test sites; and   a wafer control unit for controlling said at least one test.