Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same

Abstract

A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

What is claimed is: 
     
         1 . A method for configuring a semiconductor chip, comprising:
 placing a first cell and a second cell in a side-by-side manner, each of the first cell and the second cell including linear-shaped conductive structures formed in a first chip level and linear-shaped conductive structures formed in a second chip level, the second chip level positioned above the first chip level, the linear-shaped conductive structures formed in the first chip level oriented to extend lengthwise in a first direction, the linear-shaped conductive structures formed in the second chip level oriented to extend lengthwise in the first direction,   wherein the linear-shaped conductive structures in the first chip level are positioned along virtual lines of a first virtual grate, and wherein the linear-shaped conductive structures in the second chip level are positioned along virtual lines of a second virtual grate,   wherein virtual lines of the first virtual grate extend in the first direction and are separated by a first pitch, and wherein virtual lines of the second virtual grate extend in the first direction are separated by a second pitch,   wherein the first pitch and the second pitch are related by a factor that is a ratio of integers, and wherein the first virtual grate and the second virtual grate are positioned relative to each other such that some virtual lines of the second virtual grate periodically overlap some virtual lines of the first virtual grate,   wherein a virtual line of the first virtual grate is positioned in the first chip level of the second cell at a first index distance from a boundary of the second cell that is positioned next to the first cell, the first index distance defined to provide for continuation of the first virtual grate in accordance with the first pitch from the first chip level of the first cell into the first chip level of the second cell, and   wherein a virtual line of the second virtual grate is positioned in the second chip level of the second cell at a second index distance from the boundary of the second cell that is positioned next to the first cell, the second index distance defined to provide for continuation of the second virtual grate in accordance with the second pitch from the second chip level of the first cell into the second chip level of the second cell.   
     
     
         2 . The method as recited in  claim 1 , wherein each of the first index distance and the second index distance is measured in a second direction perpendicular to the first direction. 
     
     
         3 . The method as recited in  claim 2 , wherein the first index distance is either equal to zero or equal to one-half of the first pitch. 
     
     
         4 . The method as recited in  claim 3 , wherein the first chip level is a gate electrode level, and wherein the second chip level is a second interconnect level. 
     
     
         5 . The method as recited in  claim 4 , wherein the ratio of integers is 4/3. 
     
     
         6 . The method as recited in  claim 5 , wherein the first index distance is zero and the second index distance is zero. 
     
     
         7 . The method as recited in  claim 5 , wherein the first index distance is zero and the second index distance is zero. 
     
     
         8 . The method as recited in  claim 5 , wherein the first index distance is equal to one-half of the first pitch and the second index distance is equal to five-sixths of the first pitch. 
     
     
         9 . The method as recited in  claim 5 , wherein the first index distance is zero and the second index distance is equal to one-third of the first pitch. 
     
     
         10 . The method as recited in  claim 5 , wherein the first index distance is equal to one-half of the first pitch and the second index distance is equal to seven-sixths of the first pitch. 
     
     
         11 . The method as recited in  claim 5 , wherein the first index distance is zero and the second index distance is equal to two-thirds of the first pitch. 
     
     
         12 . The method as recited in  claim 5 , wherein the first index distance is equal to one-half of the first pitch and the second index distance is equal to one-sixth of the first pitch. 
     
     
         13 . The method as recited in  claim 5 , wherein the first index distance is zero and the second index distance is equal to the first pitch. 
     
     
         14 . The method as recited in  claim 5 , wherein the first index distance is equal to one-half of the first pitch and the second index distance is equal to one-half of the first pitch. 
     
     
         15 . The method as recited in  claim 5 , wherein the first index distance is zero and the second index distance is equal to one-sixth of the first pitch. 
     
     
         16 . The method as recited in  claim 5 , wherein the first index distance is equal to one-half of the first pitch and the second index distance is equal to the first pitch. 
     
     
         17 . The method as recited in  claim 5 , wherein the first index distance is zero and the second index distance is equal to one-half of the first pitch. 
     
     
         18 . The method as recited in  claim 5 , wherein the first index distance is equal to one-half of the first pitch and the second index distance is equal to four-thirds of the first pitch. 
     
     
         19 . The method as recited in  claim 5 , wherein the first index distance is zero and the second index distance is equal to five-sixths of the first pitch. 
     
     
         20 . The method as recited in  claim 5 , wherein the first index distance is equal to one-half of the first pitch and the second index distance is equal to one-third of the first pitch. 
     
     
         21 . The method as recited in  claim 5 , wherein the first index distance is zero and the second index distance is equal to seven-sixths of the first pitch. 
     
     
         22 . The method as recited in  claim 5 , wherein the first index distance is equal to one-half of the first pitch and the second index distance is equal to two-thirds of the first pitch.