Methods to send extra information in-band on inter-integrated circuit (i2c) bus

Abstract

System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.

What is claimed is: 
     
         1 . A method of data communication on a serial bus, comprising:
 transmitting or receiving data through a first line of a serial bus in accordance with timing provided by a clock signal transmitted on a second line of the serial bus; and   communicating one or more bits of information over the second line of the serial bus encoded in differences in timing of pulses provided in the clock signal.   
     
     
         2 . The method of  claim 1 , wherein a bit of information that has a first value is communicated over the clock signal in a pulse that has a first duration and a bit of information that has a second value is communicated over the clock signal in a pulse that has a second duration, the first duration being greater than the second duration. 
     
     
         3 . The method of  claim 2 , and further comprising:
 operating the serial bus in accordance with an Inter-Integrated Circuit (I2C) protocol while communicating the one or more bits of information over the second line of the serial bus,   wherein the first duration exceeds a minimum high period for an SCL clock specified by the I2C protocol and the second duration exceeds a minimum low period for an SCL clock specified by the I2C protocol.   
     
     
         4 . The method of  claim 1 , wherein the one or more bits of information are communicated in pulses that have a duration that is less than a maximum duration specified by the I2C protocol for a spike that is to be ignored by a receiving device. 
     
     
         5 . The method of  claim 4 , wherein the maximum duration specified by the I2C protocol for the spike is 50 nanoseconds. 
     
     
         6 . The method of  claim 1 , wherein an input filter of a receiver is configured to suppress pulses that have a duration that is less than 50 nanoseconds. 
     
     
         7 . The method of  claim 1 , wherein the one or more bits of information are communicated over the second line of the serial bus while a first byte of data is transmitted or received through the first line of the serial bus. 
     
     
         8 . The method of  claim 7 , wherein the one or more bits of information communicated over the second line of the serial bus includes a second byte of data. 
     
     
         9 . The method of  claim 1 , wherein the one or more bits of information communicated over the second line of the serial bus includes a control bit. 
     
     
         10 . The method of  claim 1 , wherein the one or more bits of information are communicated over the second line of the serial bus between frames of data exchanged over the first line of a serial bus. 
     
     
         11 . An apparatus, comprising:
 an interface circuit that couples the apparatus to a serial bus and that is configured to transmit or receive data through a first line of a serial bus in accordance with timing provided by a clock signal transmitted on a second line of the serial bus; and   a pulse-width modulation encoder configured to provide one or more bits of information to be transmitted by the interface circuit over the second line of the serial bus encoded in differences in timing of pulses provided in the clock signal.   
     
     
         12 . The apparatus of  claim 11 , wherein a bit of information that has a first value is communicated over the clock signal in a pulse that has a first duration and a bit of information that has a second value is communicated over the clock signal in a pulse that has a second duration, the first duration being greater than the second duration. 
     
     
         13 . The apparatus of  claim 12 , and further comprising a controller configured to:
 operate the serial bus in accordance with an Inter-Integrated Circuit (I2C) protocol while communicating the one or more bits of information over the second line of the serial bus,   wherein the first duration exceeds a minimum high period for an SCL clock specified by the I2C protocol and the second duration exceeds a minimum low period for an SCL clock specified by the I2C protocol.   
     
     
         14 . The apparatus of  claim 11 , wherein the one or more bits of information are communicated in pulses that have a duration that is less than a maximum duration specified by the I2C protocol for a spike that is to be ignored by a receiving device. 
     
     
         15 . The apparatus of  claim 14 , wherein the maximum duration specified by the I2C protocol for the spike is 50 nanoseconds. 
     
     
         16 . The apparatus of  claim 11 , wherein an input filter of a receiver is configured to suppress pulses that have a duration that is less than 50 nanoseconds. 
     
     
         17 . The apparatus of  claim 11 , wherein the one or more bits of information are communicated over the second line of the serial bus while a first byte of data is transmitted or received over the first line of the serial bus. 
     
     
         18 . The apparatus of  claim 17 , wherein the one or more bits of information communicated over the second line of the serial bus includes a second byte of data. 
     
     
         19 . The apparatus of  claim 11 , wherein the one or more bits of information communicated over the second line of the serial bus includes a control bit. 
     
     
         20 . The apparatus of  claim 11 , wherein the one or more bits of information are communicated over the second line of the serial bus between frames of data exchanged over the first line of the serial bus. 
     
     
         21 . A method of data communication on a serial bus, comprising:
 transmitting or receiving data through a first line of a serial bus in accordance with timing provided by a clock signal received on a second line of the serial bus; and   decoding one or more bits of information from the clock signal, wherein the one or more bits of information are encoded in differences in timing of pulses provided in the clock signal.   
     
     
         22 . The method of  claim 21 , wherein a bit of information that has a first value is communicated over the clock signal in a pulse that has a first duration and a bit of information that has a second value is communicated over the clock signal in a pulse that has a second duration, the first duration being greater than the second duration. 
     
     
         23 . The method of  claim 22 , and further comprising:
 operating the serial bus in accordance with an Inter-Integrated Circuit (I2C) protocol while communicating the one or more bits of information over the second line of the serial bus,   wherein the first duration exceeds a minimum high period for an SCL clock specified by the I2C protocol and the second duration exceeds a minimum low period for an SCL clock specified by the I2C protocol.   
     
     
         24 . The method of  claim 21 , wherein the one or more bits of information are communicated over the second line of the serial bus while a first byte of data is transmitted or received through the first line of the serial bus, and wherein the one or more bits of information communicated over the second line of the serial bus includes a second byte of data. 
     
     
         25 . The method of  claim 21 , wherein the one or more bits of information communicated over the second line of the serial bus includes a control bit. 
     
     
         26 . An apparatus, comprising:
 an interface circuit configured to transmit or receive data through a first line of a serial bus in accordance with timing provided by a clock signal transmitted on a second line of the serial bus; and   a pulse-width modulation decoder configured to decode one or more bits of information from the clock signal, wherein the one or more bits of information are encoded in differences in timing of pulses provided in the clock signal.   
     
     
         27 . The apparatus of  claim 26 , wherein a bit of information that has a first value is communicated over the clock signal in a pulse that has a first duration and a bit of information that has a second value is communicated over the clock signal in a pulse that has a second duration, the first duration being greater than the second duration. 
     
     
         28 . The apparatus of  claim 27 , and further comprising a controller configured to:
 operate the interface circuit in accordance with an Inter-Integrated Circuit (I2C) protocol while communicating the one or more bits of information over the second line of the serial bus,   wherein the first duration exceeds a minimum high period for an SCL clock specified by the I2C protocol and the second duration exceeds a minimum low period for an SCL clock specified by the I2C protocol.   
     
     
         29 . The apparatus of  claim 26 , wherein the one or more bits of information are communicated over the second line of the serial bus while a first byte of data is transmitted or received through the first line of the serial bus, and wherein the one or more bits of information communicated over the second line of the serial bus includes a second byte of data. 
     
     
         30 . The apparatus of  claim 26 , wherein the one or more bits of information communicated over the second line of the serial bus includes a control bit.