Method and apparatus for direct access from non-volatile memory to local memory

Abstract

Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) or a discrete GPU (dGPU). In particular, a method is described for transferring data between the first memory architecture and the second memory architecture that bypasses interaction with a system memory of a processor and a root complex. A transfer command is sent from the processor, (or a host agent in the GPU or dGPU), to a first memory architecture controller. The first memory architecture controller initiates the transfer of the data directly between the first memory architecture and the second memory architecture. The method bypasses: 1) a host root complex; and 2) storing the data in the system memory and then having to transfer the data to the second memory architecture or the first memory architecture.

What is claimed is: 
     
         1 . A method for transferring data, the method comprising:
 receiving, at a first memory architecture controller associated with a first memory architecture, a data transfer command when a graphics processing unit (GPU) needs access to the first memory architecture;   initiating, by the first memory architecture controller, a data transfer directly from the first memory architecture to a second memory architecture associated with the GPU; and   transferring data directly from the first memory architecture to the second memory architecture associated with the GPU using a local switch and bypassing a host processor switch.   
     
     
         2 . The method of  claim 1 , wherein the data transfer command is sent by a host processor. 
     
     
         3 . The method of  claim 1 , wherein the data transfer command is sent by a hardware agent of the at least one GPU. 
     
     
         4 . The method of  claim 1 , further comprising:
 receiving, at the first memory architecture controller associated with the first memory architecture, another data transfer command when the GPU needs access to the first memory architecture;   initiating, by the first memory architecture controller, a data transfer directly from the second memory architecture to the first memory architecture; and   transferring data directly from the second memory architecture to the first memory architecture associated with the GPU using the local switch and bypassing the host processor switch.   
     
     
         5 . The method of  claim 1 , wherein the first memory architecture controller is a non-volatile memory (NVM) controller and the first memory architecture is a NVM. 
     
     
         6 . The method of  claim 5 , wherein the second memory architecture is a local memory. 
     
     
         7 . An apparatus for transferring data, comprising:
 at least one first memory architecture;   a first memory architecture controller connected with each first memory architecture;   at least one graphics processing unit (GPU);   a second memory architecture associated with each GPU; and   a local switch coupled to each first memory architecture controller and the at least one GPU,   wherein the at least one first memory architecture controller:
 receives a data transfer command when the at least one GPU needs access to a first memory architecture associated with the at least one first memory architecture controller; 
 directly initiates a data transfer directly from the first memory architecture to the second memory architecture associated with the at least one GPU; and 
 transfers data directly from the first memory architecture to the second memory architecture associated with the at least one GPU using the local switch and bypassing a host processor switch. 
   
     
     
         8 . The apparatus of  claim 7 , wherein the data transfer command is sent by a host processor. 
     
     
         9 . The apparatus of  claim 7 , wherein the data transfer command is sent by a hardware agent of the at least one GPU. 
     
     
         10 . The apparatus of  claim 7 , wherein the at least one first memory architecture controller:
 receives another data transfer command when the at least one GPU needs access to the first memory architecture associated with the at least one first memory architecture controller;   initiates a data transfer directly from the second memory architecture associated with the at least one GPU to the first memory architecture associated with the at least one first memory architecture controller; and   transfers data directly from the local memory associated with the at least one GPU to the first memory architecture associated with the at least one first memory architecture controller using the local switch and bypassing the host processor switch.   
     
     
         11 . The apparatus of  claim 7 , wherein the first memory architecture controller is a non-volatile memory (NVM) controller and the first memory architecture is a NVM. 
     
     
         12 . The apparatus of  claim 7 , wherein the second memory architecture is a local memory. 
     
     
         13 . A system for transferring data, comprising:
 a host processor including a processor and a host processor switch; and   at least one solid state graphics (SSG) card connected to the host processor, wherein each SSG card includes:
 at least one first memory architecture; 
 a first memory architecture controller connected with each first memory architecture; 
 at least one graphics processing unit (GPU); 
 a second memory architecture associated with each GPU; 
 and 
 a local switch coupled to each first memory architecture controller and the at least one GPU, 
   wherein the host processor switch is connected to each local switch, and   wherein the at least one first memory architecture controller:
 receives a data transfer command when the at least one GPU needs access to a first memory architecture associated with the at least one first memory architecture controller; 
 directly initiates a data transfer directly from the first memory architecture to the second memory architecture associated with the at least one GPU; and 
 transfers data directly from the first memory architecture to the second memory architecture associated with the at least one GPU using the local switch and bypassing the host processor switch. 
   
     
     
         14 . The system of  claim 13 , wherein the data transfer command is sent by the host processor. 
     
     
         15 . The system of  claim 13 , wherein the data transfer command is sent by a hardware agent of the at least one GPU. 
     
     
         16 . The system of  claim 13 , wherein the at least one first memory architecture controller:
 receives another data transfer command when the at least one GPU needs access to the first memory architecture associated with the at least one first memory architecture controller;   initiates a data transfer directly from the second memory architecture associated with the at least one GPU to the first memory architecture associated with the at least one first memory architecture controller; and   transfers data directly from the second memory architecture associated with the at least one GPU to the first memory architecture associated with the at least one first memory architecture controller using the local switch and bypassing the host processor switch.   
     
     
         17 . The system of  claim 13 , wherein the first memory architecture controller is a non-volatile memory (NVM) controller and the first memory architecture is a NVM. 
     
     
         18 . The system of  claim 13 , wherein the second memory architecture is a local memory. 
     
     
         19 . A computer readable non-transitory medium including instructions which when executed in a processing system cause the processing system to execute a method for transferring data, the method comprising the steps of:
 receiving, at a first memory architecture controller associated with a first memory architecture, a data transfer command when a graphics processing unit (GPU) needs access to the first memory architecture;   initiating, by the first memory architecture controller, a data transfer directly from the first memory architecture to a second memory architecture associated with the GPU; and   transferring data directly from the first memory architecture to the second memory architecture associated with the GPU using a local switch and bypassing a host processor switch.   
     
     
         20 . The computer readable non-transitory medium of  claim 19 , wherein the data transfer command is sent by a host processor. 
     
     
         21 . The computer readable non-transitory medium of  claim 19 , wherein the data transfer command is sent by a hardware agent of the at least one GPU. 
     
     
         22 . The computer readable non-transitory medium of  claim 19 , the method further comprising the steps of:
 receiving, at the first memory architecture controller, another data transfer command when the at least one GPU needs access to the first memory architecture associated with the at least one first memory architecture controller;   initiating, by the first memory architecture controller, a data transfer directly from the second memory architecture associated with the at least one GPU to the first memory architecture associated with the at least one first memory architecture controller; and   transferring data directly from the second memory architecture associated with the at least one GPU to the first memory architecture associated with the at least one first memory architecture controller using the local switch and bypassing the host processor switch.