Multi-Voltage Complementary Metal Oxide Semiconductor Integrated Circuits Based On Always-On N-Well Architecture

Abstract

Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. An MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.

What is claimed is: 
     
         1 . A method for disposing always-on taps (ATAPs) for a multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuit (IC), comprising:
 determining a maximum allowable tap spacing value (X) dictated by a semiconductor technology used to fabricate the MV CMOS IC;   determining a metal pitch value (Y) of a plurality of metal stripes of a global power grid according to a physical design of the MV CMOS IC;   determining whether X is not smaller than Y; and   in response to a determination that X is not smaller than Y, disposing the ATAPs along and directly under the plurality of metal stripes with a spacing between adjacent ATAPs not larger than X.   
     
     
         2 . The method of  claim 1 , further comprising:
 in response to a determination that X is smaller than Y, disposing each of the ATAPs with a distance from one or more adjacent ATAPs not larger than X.   
     
     
         3 . The method of  claim 2 , wherein the ATAPs are disposed in a linear fashion with respect to the global power grid. 
     
     
         4 . The method of  claim 2 , wherein the ATAPs are disposed in a staggered fashion with respect to the global power grid. 
     
     
         5 . The method of  claim 2 , wherein the maximum allowable tap spacing value (X) is dictated based on a set of latch-up design rules. 
     
     
         6 . The method of  claim 2 , wherein the determining of the metal pitch value (Y) comprises determining the metal pitch value (Y) by a largest value of a center-to-center distance between any two adjacent metal stripes of the plurality of metal stripes of the global power grid.