3d chip assemblies using stacked leadframes

Abstract

A stacked-chip assembly including a plurality of IC chips or die that are stacked, and a plurality of stacked leads. Leads from separate leadframes may be bonded together so as to tie corresponding metal features of the various chips to a same ground, signal, or power rail. Each leadframe may include a center paddle, which is disposed between two chips in the stack. The center paddle may function as one or more of a thermal conduit and common electrical rail (e.g., ground). The leadframes may be employed without the use of any bond wires with leads bonded directly to bond pads of the chips. A first IC chip may be mounted to a base leadframe and subsequent die-attach leadframes and IC chips are stacked upon the first IC chip and base leadframe. The die-attach leadframes may be iteratively bonded to an underlying leadframe and the bonded stacked leads stamped out of their respective leadframe sheets.

What is claimed is: 
     
         1 . An integrated circuit (IC) chip assembly, comprising:
 a first IC chip;   a second IC chip in a stack with the first IC chip;   a paddle between the first and second IC chips, wherein the paddle comprises metal and includes a paddle end that is coupled to at least one of a metal feature at a periphery of the stack, or a heat sink.   
     
     
         2 . The IC chip assembly of  claim 1 , wherein the paddle end is coupled to a metal feature at a periphery of the stack, and wherein the paddle makes electrical contact to a metal feature on one or both of the first and second IC chips. 
     
     
         3 . The IC chip assembly of  claim 2 , wherein the paddle electrically couples each of the IC chips to a common reference voltage rail. 
     
     
         4 . The IC chip assembly of  claim 2 , further comprising a substrate including a ground pad, and where the paddle end is bonded to the ground pad. 
     
     
         5 . The IC chip assembly of  claim 1 , wherein:
 the paddle is a first paddle and the assembly further comprises a second paddle;   the second paddle comprises a metal,   a paddle end of the first paddle is bonded to a paddle end of the second paddle at the periphery of the chip stack.   
     
     
         6 . The IC chip assembly of  claim 1 , further comprising a base paddle coupled to a side of the first chip opposite the paddle between the first and second chips, and wherein an area of the base paddle is larger than an area of the paddle between the first and second chips. 
     
     
         7 . The IC chip assembly of  claim 1 , further comprising a first lead and a second lead, the first lead electrically coupled to at least the first IC chip; and
 a second lead electrically coupled to at least the second IC chip, and bonded to the second lead at the periphery of the chip stack.   
     
     
         8 . The IC chip of  claim 7 , wherein the paddle is electrically isolated from at least one of the first or second leads. 
     
     
         9 . The IC chip of  claim 8 , further comprising a substrate including a plurality of signal pads; and
 wherein the first lead is electrically coupled to one of the signal pads.   
     
     
         10 . The IC platform of  claim 12 , wherein the IC chips comprise a plurality of NAND flash memory chips. 
     
     
         11 . The IC chip assembly of  claim 1 , further comprising a die-attach paste or film disposed between at least one of the leads and the first or second IC chip. 
     
     
         12 . An integrated circuit (IC) platform, comprising:
 a substrate including a plurality of signal pads;   three of more memory chips in a stack;   a paddle between each of the memory chips, wherein:   the paddle comprises a metal and includes one or more paddle ends;   a paddle end of each paddle is coupled to at least one of a metal feature of the substrate at a periphery of the stack, or a heat sink; and   a plurality of signal leads electrically coupled to each of the chips and to the signal pads.   
     
     
         13 . The IC platform of  claim 12 , wherein the metal feature comprises a ground pad and wherein the paddles are electrically isolated from the signal leads. 
     
     
         14 . The IC platform of  claim 12 , wherein the signal leads comprise a plurality of a die-attach leads, a first end of spatially co-located ones of the die-attach leads bonded together at the periphery of the stack, and a second end of the die-attach leads bonded to a metal feature on separate ones of the chips. 
     
     
         15 . The IC platform of  claim 12 , wherein the memory chips are NAND memory chips with substantially the same footprint and the same pin-out pad locations. 
     
     
         16 . A method of assembling an integrated circuit (IC) chip stack, the method comprising:
 attaching a first leadframe to a first IC chip, the first leadframe including a first paddle under the first IC chip;   attaching a second leadframe to a second IC chip, the second leadframe including a second paddle under the second IC chip;   stacking the first and second leadframes with the second paddle between the first and second first and second IC chips;   bonding ends of the first and second paddle together; and   singulating the chip stack from the stacked leadframes at a location beyond the bonded paddle ends to maintain electrical continuity between the first and second paddles.   
     
     
         17 . The method of  claim 16 , further comprising bonding first leads of the first leadframe to corresponding second leads of the second leadframe that are stacked over the first leads, the bonded first leads further coupled to the first IC chip, and the bonded second leads further coupled to the second IC chip. 
     
     
         18 . The method of  claim 17 , wherein:
 attaching the first leadframe to the first chip further comprises bonding the first leads to metal features on a front-side surface of the first IC chip;   attaching the second leadframe further comprises bonding the second leads to metal features on a front-side surface of the second IC chip; and   bonding the first leads to the second leads further comprises wedge-bonding the second leads to the first leads at a location beyond an edge of the first and second IC chips.   
     
     
         19 . The method of  claim 17 , further comprising:
 adhering a back-side surface of the first IC chip to the paddle of the first leadframe; and   bonding the first leads to corresponding leads of a base leadframe prior to bonding the second leads to the first leads.   
     
     
         20 . The method of  claim 19 , further comprising adhering a back-side surface a third IC chip to a paddle of the base leadframe before bonding the first leadframe to the base leadframe.