Translating Media Access Control (MAC) Addresses In A Network Hierarchy

Abstract

In one embodiment a method includes receiving a packet including a destination media access control (MAC) address field having a MAC address of a hypervisor and a destination Internet protocol (IP) address field having an IP address of a virtual machine (VM) coupled to the hypervisor. The method further determines a MAC address of the VM using the IP address of the VM and applies the VM MAC address to the destination MAC address field of the packet to forward the packet to the VM.

1 - 19 . (canceled) 
     
     
         1 . A system for routing network patents comprising:
 a top of rack (TOR) switch, the TOR switch including an address memory, an external network port, a plurality of local network ports, and an internal switching network programmably and communicably connecting the external and local network ports;   a first computing device, the first computing device including a processor, a memory, and a first network interface communicably coupled to a local network port on the TOR switch via a first local network link;   wherein the first computing device includes computer instructions implementing a first hypervisor loaded into the memory and being executed by the processor, the hypervisor including an address masking component;   wherein the first network interface is associated with a first layer 2 (L2) address and a first layer 3 (L3) address;   wherein the first computing device includes a first virtual environment and a second virtual environment, each virtual environment being managed by the first hypervisor, each of the first and second virtual environments, the first and second virtual environments including first and second virtual network interfaces (VNI), respectively, each VNI with associated L2 and L3 addresses, and each VNI communicably coupled to the first network interface;   wherein the address masking component modifies a packet received from the first VNI such that the packet contains the L3 address of the first VNI and the L2 address of the first network interface prior to the packet being communicated to the TOR switch.   
     
     
         2 . The system of  claim 1 , wherein the address masking component modifies a received packet containing the L3 address of the first VNI and the L2 address of the first network interface such that the packet contains the L2 and L3 addresses of the first VNI prior to the packet being communicated to the first VNI. 
     
     
         3 . The system of  claim 1 , wherein the address masking component modifies a packet emitted from the second VNI such that the packet contains the L3 address of the second VNI and the L2 address of the first network interface prior to being communicated to the TOR switch. 
     
     
         4 . The system of  claim 1 , wherein the address memory in the TOR switch associates the L3 address of the first VNI with the L2 address of the first network interface. 
     
     
         5 . The system of  claim 4 , wherein the address memory in the TOR switch also associates the L3 address of the second VNI with the L2 address of the first network interface. 
     
     
         6 . The system of  claim 5 , wherein the first network interface listens on the local network link in promiscuous mode and passes any packets matching the L2 address of the first network interface to the address masking component. 
     
     
         7 . The system of  claim 1  wherein the address memory is a content addressable memory. 
     
     
         8 . The system of  claim 1 , further comprising a provisioning manager programmatically coupled to the TOR switch, the provisioning manager operable to associate the L3 address of the first VNI with the L2 address of the first network interface in the address memory of the TOR switch. 
     
     
         9 . The system of  claim 8 , wherein the provisioning manager is further operable to create a new association in the address memory in the TOR switch between the L3 address of a third virtual environment being managed by the first hypervisor and the L2 address of the first network interface upon the instantiation the third virtual environment. 
     
     
         10 . A system for routing network patents comprising:
 a top of rack (TOR) switch, the TOR switch including a first address memory, a first external network port, a first plurality of local network ports, and a first internal switching network programmably and communicably connecting the external and local network ports, and an address masking component, the first external network port having associated layer 2 (L2) and layer 3 (L3) addresses;   a plurality of network traffic sources communicably coupled to the local network ports, each network traffic source having associated layer 2 (L2) and layer 3 (L3) addresses;   a second switch, the second switch including a second address memory, and a plurality of switch network ports, and an internal switching network programmably and communicably connecting the plurality of switch network ports;   a layer 1 (L1) connection communicably coupling the first external network port on the TOR switch with a switch port from the plurality of switch network ports;   wherein the address masking component modifies a packet received from a network traffic source such that the packet contains the L3 address of the network traffic source and the L2 address of the first external network port prior to the packet being communicated from the TOR switch to the second switch.   
     
     
         11 . The system of  claim 10 , wherein the address masking component modifies a received packet containing the L3 address of a first network traffic source and the L2 address of the first external network port such that the packet contains the L2 and L3 addresses associated with the first network traffic source prior to the packet being communicated to over the internal switching network to a local network port. 
     
     
         12 . The system of  claim 11 , wherein the address masking component modifies a packet emitted from a second network traffic source such that the packet contains the L3 address of the second network traffic source and the L2 address of the first external network port prior to the packet being communicated from the TOR switch to the second switch. 
     
     
         13 . The system of  claim 10 , wherein the second address memory associates the L3 address of a first network traffic source with the L2 address of the first external network port. 
     
     
         14 . The system of  claim 13 , wherein the address memory in the second switch also associates a second L3 address from a second network traffic source with the L2 address of the first external network port. 
     
     
         15 . A packet switching fabric, comprising:
 first and second switching components, each switching component including an address memory, a plurality of ingress network ports, an egress network port, an addressing masking component, and a internal switching network programmably and communicably connecting the ingress and egress network ports, each ingress and egress network port having associated layer 2 (L2) and layer 3 (L3) addresses; the first and second switching components being communicably coupled to each other;   a plurality of network traffic sources communicably coupled to the ingress ports, each network traffic source having associated layer 2 (L2) and layer 3 (L3) addresses;   wherein a packet traveling one of the plurality of network traffic sources to the second switching component will be modified at least twice by replacing the L2 address included in the packet with a new L2 address, but keeping the L3 address the same.   
     
     
         16 . The system of  claim 15 , wherein the address memories in the first and second switching component are content addressable memories. 
     
     
         17 . The system of  claim 15 , wherein a number of L2 addresses lower than the total number of network traffic sources within the system is cached in the first and second address memories.