Semiconductor device and method for prefetching to cache memory

Abstract

A microcontroller includes multiple ways each including only one tag. When a first access and a second access are accesses performed in succession to consecutive addresses, and when the second access is the access through a first way, a cache controller performs the following operations: prefetching to the way whose tag value is smaller by 1 than the tag value corresponding to the first way when the second access is the access in the direction in which the address is incremented with respect to the first access; and prefetching to the way whose tag value is greater by 1 than the tag value corresponding to the first way when the access is in the direction in which the address is decremented.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a processor;   a memory; and   a cache memory coupled between the processor and the memory, and including a data cache, an instruction cache and a cache controller;   wherein the data cache includes a plurality of tags, and a plurality of ways each of which can store a plurality of data of consecutive addresses of the memory in which a tag value stored in each tag of the plurality of tags is taken as a reference address,   wherein each of the plurality of ways is provided with an address change direction flag that indicates a direction in which the address is either incremented or decremented with respect to the last two accesses to the way,   wherein when a first access and a second access are accesses that are performed in succession to consecutive addresses from the processor to the memory, and when the second access is the access through a first way of the plurality of ways, the cache controller is configured to determine presence or absence of a second way having a same address change direction flag as an address change direction flag of the first way among the plurality of ways and prefetch data to the second way based on a result of the determination of the presence or absence of the second way,   wherein the second way has a tag value which is continuous with a tag value of the first way in a direction opposite to a direction that the same address change direction flag indicates, and   wherein the data prefetched to the second way is data indicated by a tag value which is continuous with the tag value of the first way in the direction that the same address change direction flag indicates.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein when the second access is the access to the same way and the same tag value as in the case of the first way, the cache controller is configured to allow setting of the address change direction flag when a target address of the second access is smaller than a target address of the first access.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein, if it is a cache miss, the cache controller is configured to allow performing a cache fill in units of the data length obtained by dividing the total data length of the data stored in the way by an integer.   
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein in the cache controller, the each of the ways is provided with a valid flag in units of the data length of the cache fill, and   wherein when a cache miss occurs, the cache controller is configured to allow clearing of all the valid flags corresponding to the target way of the cache fill, and allow setting of the valid flag corresponding to the cache fill data.   
     
     
         5 . The semiconductor device according to  claim 4 ,
 wherein the cache controller is configured to allow prefetching of data into an area within the first way in which the corresponding valid flag is not set, in the direction indicated by the address change direction flag corresponding to the first way, after the second access.   
     
     
         6 . The semiconductor device according to  claim 5 ,
 wherein when the address change direction flag corresponding to the second way and the address change direction flag corresponding to the first way match each other, and when the tag value corresponding to the second way is continuous in the direction opposite to the direction that the address change direction flag indicates with respect to the tag value corresponding to the first way, the cache controller is configured to allow prefetching of data to the second way after the prefetching of data to the area within the first way, and   wherein when the address change direction flag corresponding to the second way does not match the address change direction flag corresponding to the first way, or when the tag value corresponding to the second way is not continuous in the direction opposite to the direction that the address change direction flag indicates with respect to the tag value corresponding to the first way, the cache controller is configured, after the prefetching of data to the area within the first way, to allow prefetching of data to the area within the first way in the direction opposite to the direction indicated by the address change direction flag corresponding to the first way after the second access within the first way.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein the processor is configured to allow performing the access following the second access, after the second access is completed and before the cache memory completes the prefetch.   
     
     
         8 . The semiconductor device according to  claim 1 ,
 wherein each of the ways is configured to allow caching of data of an arbitrary address in the memory.   
     
     
         9 . The semiconductor device according to  claim 1 ,
 wherein the cache controller includes an address control unit and a data control unit,   wherein the address control unit is coupled to the processor via an address bus, and,   wherein the data control unit is coupled to the processor via a data bus.