System and method for electrical boot-device-reset signals

Abstract

Systems and methods for providing accelerated loading of operating system and application programs upon system boot or application launch are disclosed. In one aspect, a method for providing accelerated loading of an operating system comprises the steps of: maintaining a list of boot data used for booting a computer system; preloading the boot data upon initialization of the computer system; and servicing requests for boot data from the computer system using the preloaded boot data. In another aspect, a method for providing accelerated launching of an application program comprises the steps of: maintaining a list of application data associated with an application program; preloading the application data upon launching the application program; and servicing requests for application data from a computer system using the preloaded application data.

1 .- 20 . (canceled) 
     
     
         21 . A system for generating a boot device reset signal, the system comprising:
 a first node for receiving a power supply monitoring signal;   a second node for receiving a system cold boot reset request; and   a power supply monitor dual time constant integrator coupled to the first node;   wherein the system is configured to:   perform a logical OR operation of an output signal of the power supply monitor dual time constant integrator and the system cold boot reset request; and   electrically differentiate the logical OR of the output signal of the power supply monitor dual time constant integrator and the system cold boot reset request to generate an electrically differentiated signal.   
     
     
         22 . The system of  claim 21 , wherein the electrically differentiated signal is utilized to set a cold boot flag. 
     
     
         23 . The system of  claim 21 , wherein the power supply monitor dual time constant integrator comprises a single capacitor. 
     
     
         24 . The system of  claim 21 , wherein the power supply monitor dual time constant integrator comprises a charge resistor and a discharge resistor. 
     
     
         25 . The system of  claim 24 , wherein the resistances of the charge resistor and the discharge resistor are at least one order of magnitude apart. 
     
     
         26 . The system of  claim 21 , further comprising a differentiator for performing the electrical differentiation, said differentiator comprising a capacitor and a resistor. 
     
     
         27 . The system of  claim 21 , wherein the power supply monitor dual time constant integrator comprises a logical combination of power supply voltages to create a power sense signal. 
     
     
         28 . The system of  claim 27 , wherein the logical combination ensures that power has been applied in a proper sequence. 
     
     
         29 . The system of  claim 27 , wherein the combination of power supply voltages includes one or more of: +5 volts, +3.3 volts, +1.8 volts, +1.5 volts, +12 volts, −12 volts. 
     
     
         30 . The system of  claim 21 , further comprising a Schmidt trigger for providing noise rejection to the electrically differentiated signal. 
     
     
         31 . A method for creating a boot device reset, the method comprising:
 performing a logical OR operation of a power supply monitoring signal generated from the output of the power supply monitor dual time constant integrator with a system cold boot reset request; and   electrically differentiating the logical OR of the cold boot system reset signal and the output of the power supply monitor dual time constant integrator.   
     
     
         32 . The method of  claim 31 , wherein the electrically differentiated signal generated from the logical OR of the cold boot system reset signal and the output of the power supply monitoring dual time constant integrator is utilized to set a cold boot flag. 
     
     
         33 . The method of  claim 31 , wherein the dual time constant integrator utilizes a single capacitor. 
     
     
         34 . The method of  claim 31 , wherein the dual time constant integrator utilizes a charge resistor and a discharge resistor. 
     
     
         35 . The method of  claim 34 , wherein the resistances of the charge resistor and the discharge resistor are at least one order of magnitude apart. 
     
     
         36 . The method of  claim 31 , wherein the time constant to charge and the time constant to discharge the dual time constant integrator are at least one order of magnitude apart. 
     
     
         37 . The method of  claim 31 , wherein the differentiator is comprised of a capacitor and a resistor. 
     
     
         38 . The method of  claim 31 , wherein the power supply monitor utilizes a logical combination of power supply voltages to create a power sense signal. 
     
     
         39 . The method of  claim 38 , wherein the specific logic combination ensures that the power has been applied in the proper sequence. 
     
     
         40 . The method of  claim 38 , wherein the combination of power supply voltages includes one or more of: +5 volts, +3.3 volts, +1.8 volts, +1.5 volts, +12 volts, −12 volts. 
     
     
         41 . The method of  claim 31 , wherein a Schmidt trigger is utilized in conjunction with the logical OR function for noise rejection. 
     
     
         42 . A method for creating an electrical boot device reset, the method comprising:
 performing a logical OR of an optional system reset signal with an optional expansion bus reset signal and with an optional commanded warm boot reset request; and   differentiating the logical OR of the optional system reset signal with the optional expansion bus reset signal and with the optional commanded warm boot reset request.   
     
     
         43 . The method of  claim 42 , wherein the differentiated logical OR of the optional system reset signal with the optional expansion bus reset signal and with the optional commanded warm boot reset request is utilized to create a boot device reset. 
     
     
         44 . The method of  claim 42 , wherein the differentiated logical OR of the optional system reset signal with the optional expansion bus reset signal and with the optional commanded warm boot reset request is utilized to set a warm boot flag. 
     
     
         45 . The method of  claim 42 , wherein the differentiated logical OR of the optional system reset signal with the optional expansion bus reset signal and with the optional commanded warm boot reset request is utilized to create a boot device reset and set a warm boot flag. 
     
     
         46 . A boot management circuit comprising:
 a set of one or more inputs, each input operable to provide to the boot management circuit a signal selected from a power supply monitoring signal, a system cold boot reset request signal, a commanded warm boot reset request signal, a system reset signal, or an expansion bus reset signal; and   one or more of a boot device reset signal output, a system reset signal output, a warm boot flag signal output, or a cold boot flag signal output,   wherein the boot management circuit is operable to provide an indication of at least one of:
 a cold boot request at the cold boot flag signal output based on receipt of at least one of the power supply monitoring signal or the system cold boot reset signal, 
 a warm boot request at the warm boot flag signal output based on receipt of a commanded warm boot request signal, 
 a cold boot request at the cold boot flag signal output based on receipt of either the system reset signal or the expansion bus reset signal, and further based on the power supply monitoring signal being below a threshold value, or 
 a warm boot request at the warm boot flag signal output based on receipt of either the system reset signal or the expansion bus reset signal, and further based on the power supply monitoring signal being above the threshold value. 
   
     
     
         47 . The boot management circuit of  claim 46 , further comprising:
 a power supply sense circuit for receiving the power supply monitoring signal;   a first logic device operable to output a logical OR of an output of the power supply sense circuit and the system cold boot reset request signal; and   a first differentiator for receiving the output logical OR and for generating a pulse for creating the boot device reset signal.   
     
     
         48 . The boot management circuit of  claim 47 , wherein the power supply sense circuit comprises a dual time constant integrator having a first capacitor and a first resistor that establish a charge time constant, and having a second resistor, that, with the first capacitor, establishes a discharge time constant. 
     
     
         49 . The boot management circuit of  claim 47 , wherein the second resistor is at least an order of magnitude lower than the first resistor. 
     
     
         50 . The boot management circuit of  claim 48 , wherein the power sense circuit includes a jumper for bypassing the dual time constant integrator. 
     
     
         51 . The boot management circuit of  claim 47 , wherein the first logic device is a Schmidt AND gate. 
     
     
         52 . The boot management circuit of  claim 47 , further comprising:
 a system reset circuit having a first node for outputting the system reset signal or the expansion bus reset signal and having a second node for outputting the commanded warm boot reset request signal;   a second logic device operable to output a logical OR of signals at the first and second nodes; and   second differentiator for receiving the output logical OR of the signals at the first and second nodes; and   a third logical device operable to output a logical OR of the first and second differentiators.   
     
     
         53 . The boot management circuit of  claim 52 , further comprising a flip-flop for receiving outputs of the first and second differentiators and generating signals at the warm boot flag and cold boot flag signal outputs. 
     
     
         54 . The boot management circuit of  claim 47 , wherein the power supply sense circuit is configured to sense power supply voltages selected from one or more of: +5 volts, +3.3 volts, +1.8 volts, +1.5 volts, +12 volts, and −12 volts.