Solid state device miniaturization

Abstract

One or more example embodiments of miniaturized electric devices are disclosed. In some example embodiments, the electric device includes a first thin substrate layer and a second thin substrate layer positioned above the first thin substrate layer. The electric device further includes one or more components electrically coupled to the first thin substrate layer. An overmold compound is deposited covering the one or more components between the first thin substrate and the second thin substrate. The electric device further includes one or more through mold vias that electrically and communicatively connect the first thin substrate layer and the second thin substrate layer.

1 . (canceled) 
     
     
         2 . A memory device, comprising:
 a first substrate layer;   a second substrate layer positioned proximate the first substrate layer such that a space is formed between the first substrate layer and the second substrate layer, wherein the second substrate layer is in electrical communication with the first substrate layer;   one or more components positioned in the space;   an overmold compound forming a direct interface with the one or more components; and   one or more edge connectors coupled to an exterior surface of a first end of the memory device and positioned proximate the edge of the first substrate layer, wherein the one or more edge connectors are configured to be in electrical communication with the one or more components.   
     
     
         3 . The memory device of  claim 2 , wherein the one or more components includes a die stack. 
     
     
         4 . The memory device of  claim 2 , wherein a portion of the one or more components extends through a hole in the second substrate. 
     
     
         5 . The memory device of  claim 2 , wherein at least one of the one or more components are positioned within a footprint of a hole in the second substrate. 
     
     
         6 . The memory device of  claim 2 , wherein the one or more components includes NAND memory or DRAM memory. 
     
     
         7 . The memory device of  claim 2 , wherein the one or more components include passive components. 
     
     
         8 . The memory device of  claim 2 , wherein the one or components positioned in the space is a first set of components, and further comprising a second set of components positioned on the second substrate. 
     
     
         9 . The memory device of  claim 2 , wherein the one or more edge connectors are coupled to the first substrate layer and the second substrate layer. 
     
     
         10 . The memory device of  claim 2 , wherein the one or more edge connectors are coplanar with an edge of the first substrate. 
     
     
         11 . The memory device of  claim 2 , further comprising one or more ground connectors. 
     
     
         12 . The memory device of  claim 11 , wherein the one or more ground connectors are coupled to an exterior surface of a second end of the memory device and positioned proximate the edge of the first substrate layer. 
     
     
         13 . The memory device of  claim 2 , wherein the one or more ground connectors are coplanar with an edge of the first substrate. 
     
     
         14 . The memory device of  claim 2 , wherein the first substrate layer or the second substrate layer has a thickness of approximately 0.3 millimeters to 0.8 millimeters. 
     
     
         15 . The memory device of  claim 2 , further comprising a first via, wherein the first via is configured to allow the electrical communication between the first substrate layer and the second substrate layer. 
     
     
         16 . The memory device of  claim 15 , wherein the first via is a through mold via, and the through mold via forms a direct interface with the overmold compound. 
     
     
         17 . The memory device of  claim 15 , further comprising a second via, wherein the second via is configured to allow the electrical communication between the first substrate layer and a third substrate layer, wherein the third substrate layer is coplanar with the second substrate layer. 
     
     
         18 . An electronic system, comprising:
 a memory device, including:
 a first substrate layer; 
 a second substrate layer positioned proximate the first substrate layer such that a space is formed between the first substrate layer and the second substrate layer, wherein the second substrate layer is in electrical communication with the first substrate layer; 
 one or more components positioned in the space; 
 an overmold compound forming a direct interface with the one or more components; 
 one or more edge connectors coupled to an exterior surface of a first end of the memory device and positioned proximate the edge of the first substrate layer, wherein the one or more edge connectors are configured to be in electrical communication with the one or more components; 
   a processor in electrical communication with the memory device.   
     
     
         19 . The memory device of  claim 18 , wherein the one or more components includes a die stack. 
     
     
         20 . The memory device of  claim 18 , wherein the one or more edge connectors are coplanar with an edge of the first substrate. 
     
     
         21 . The memory device of  claim 18 , wherein the first substrate layer or the second substrate layer has a thickness of approximately 0.3 millimeters to 0.8 millimeters.