Semiconductor device and method of manufacturing the same

Abstract

An insulating film is formed such that the insulating film covers a source electrode and a gate electrode, and an opening portion exposing a portion of the source electrode and an opening portion exposing a portion of the gate electrode are formed in the insulating film. A plated layer is formed over the source electrode exposed in the opening portion, and a plated layer is formed over the gate electrode exposed in the opening portion. A source pad is formed of the portion of the source electrode exposed in the opening portion, and the plated layer, and a gate pad is formed of the portion of the gate electrode exposed in the opening portion, and the plated layer. An area of the opening portion for the gate pad is smaller than an area of the opening portion for the source pad, and a thickness of the plated layer over the gate electrode is greater than a thickness of the plated layer over the source electrode.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate;   an interlayer insulating film formed over a main surface of the semiconductor substrate;   a first conductive film pattern for a first pad formed over the interlayer insulating film and a second conductive film pattern for a second pad formed over the interlayer insulating film;   an insulating film formed over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns;   a first opening portion for the first pad, the first opening portion being formed in the insulating film and exposing a portion of the first conductive film pattern;   a second opening portion for the second pad, the second opening portion being formed in the insulating film and exposing a portion of the second conductive film pattern;   a first plated layer formed over the portion of the first conductive film pattern exposed in the first opening portion; and   a second plated layer formed over the portion of the second conductive film pattern exposed in the second opening portion,   wherein the first pad is formed of the portion of the first conductive film pattern exposed in the first opening portion, and the first plated layer,   wherein the second pad is formed of the portion of the second conductive film pattern exposed in the second opening portion, and the second plated layer,   wherein an area of the second opening portion is smaller than an area of the first opening portion, and   wherein a thickness of the second plated layer is greater than a thickness of the first plated layer.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the first and the second conductive film patterns include a conductive material containing aluminum as a main component.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein the first plated layer includes a first nickel plated layer formed over the portion of the first conductive film pattern exposed in the first opening portion,   wherein the second plated layer includes a second nickel plated layer formed over the portion of the second conductive film pattern exposed in the second opening portion, and   wherein a thickness of the second nickel plated layer is greater than a thickness of the first nickel plated layer.   
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein the thickness of the second nickel plated layer is 1.2 times or more the thickness of the first nickel plated layer.   
     
     
         5 . The semiconductor device according to  claim 3 ,
 wherein the first plated layer includes the first nickel plated layer formed over the portion of the first conductive film pattern exposed in the first opening portion, and a first gold plated layer formed over the first nickel plated layer, and   wherein the second plated layer includes the second nickel plated layer formed over the portion of the second conductive film pattern exposed in the second opening portion, and a second gold plated layer formed over the second nickel plated layer.   
     
     
         6 . The semiconductor device according to  claim 3 ,
 wherein the first plated layer includes the first nickel plated layer formed over the portion of the first conductive film pattern exposed in the first opening portion, a first palladium plated layer formed over the first nickel plated layer, and a first gold plated layer formed over the first palladium plated layer, and   wherein the second plated layer includes the second nickel plated layer formed over the portion of the second conductive film pattern exposed in the second opening portion, a second palladium plated layer formed over the second nickel plated layer, and a second gold plated layer formed over the second palladium plated layer.   
     
     
         7 . The semiconductor device according to  claim 3 ,
 wherein a power MISFET is formed in the semiconductor substrate,   wherein a drain back surface electrode is formed over a back surface opposite to the main surface of the semiconductor substrate, and   wherein the first conductive film pattern is a source conductive film pattern and the second conductive film pattern is a gate conductive film pattern.   
     
     
         8 . The semiconductor device according to  claim 1 ,
 wherein the first pad is a bonding pad for connecting a metal plate, and   wherein the second pad is a bonding pad for connecting a wire.   
     
     
         9 . The semiconductor device according to  claim 1 ,
 wherein the area of the first opening portion is nine times or more the area of the second opening portion.   
     
     
         10 . A method of manufacturing a semiconductor device, comprising the steps of:
 (a) forming an interlayer insulating film over a main surface of a semiconductor substrate;   (b) forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film;   (c) forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns;   (d) forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film; and   (e) forming a first plated layer over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer over the portion of the second conductive film pattern exposed in the second opening portion,   wherein the first pad is formed of the portion of the first conductive film pattern exposed in the first opening portion, and the first plated layer,   wherein the second pad is formed of the portion of the second conductive film pattern exposed in the second opening portion, and the second plated layer,   wherein an area of the second opening portion is smaller than an area of the first opening portion, and   wherein a thickness of the second plated layer is greater than a thickness of the first plated layer.   
     
     
         11 . The method of manufacturing a semiconductor device according to  claim 10 ,
 wherein the first and the second conductive film patterns include a conductive material containing aluminum as a main component.   
     
     
         12 . The method of manufacturing a semiconductor device according to  claim 10 ,
 wherein the first plated layer includes a first nickel plated layer,   wherein the second plated layer includes a second nickel plated layer,   wherein the step (e) includes the step of:
 (e1) forming the first nickel plated layer over the portion of the first conductive film pattern exposed in the first opening portion, and the second nickel plated layer over the portion of the second conductive film pattern exposed in the second opening portion, and 
   wherein a thickness of the second nickel plated layer is greater than a thickness of the first nickel plated layer.   
     
     
         13 . The method of manufacturing a semiconductor device according to  claim 12 ,
 wherein, in the step (e1), a film-forming speed of the second nickel plated layer is larger than a film-forming speed of the first nickel plated layer.   
     
     
         14 . The method of manufacturing a semiconductor device according to  claim 12 ,
 wherein the thickness of the second nickel plated layer is 1.2 times or more the thickness of the first nickel plated layer.   
     
     
         15 . The method of manufacturing a semiconductor device according to  claim 12 ,
 wherein the first plated layer includes the first nickel plated layer, and a first gold plated layer formed over the first nickel plated layer,   wherein the second plated layer includes the second nickel plated layer, and a second gold plated layer formed over the second nickel plated layer, and   wherein the step (e) further includes the step of:
 (e2) after the step (e1), forming the first gold plated layer over the first nickel plated layer, and the second gold plated layer over the second nickel plated layer. 
   
     
     
         16 . The method of manufacturing a semiconductor device according to  claim 12 ,
 wherein the first plated layer includes the first nickel plated layer, a first palladium plated layer formed over the first nickel plated layer, and a first gold plated layer formed over the first palladium plated layer,   wherein the second plated layer includes the second nickel plated layer, a second palladium plated layer formed over the second nickel plated layer, and a second gold plated layer formed over the second palladium plated layer, and   wherein the step (e) includes the steps of:
 (e2) after the step (e1), forming the first palladium plated layer over the first nickel plated layer, and the second palladium plated layer over the second nickel plated layer; and 
 (e3) after the step (e2), forming the first gold plated layer over the first palladium plated layer, and the second gold plated layer over the second palladium plated layer. 
   
     
     
         17 . The method of manufacturing a semiconductor device according to  claim 10 , further comprising the steps of:
 (a1) before the step (a), forming a semiconductor element in the semiconductor substrate; and   (f) after the step (e), forming a back surface electrode over a back surface opposite to the main surface of the semiconductor substrate.   
     
     
         18 . The method of manufacturing a semiconductor device according to  claim 17 ,
 wherein the semiconductor element is a power MISFET, and the first conductive film pattern is a source conductive film pattern, the second conductive film pattern is a gate conductive film pattern, and the back surface electrode is a drain back surface electrode.   
     
     
         19 . The method of manufacturing a semiconductor device according to  claim 10 ,
 wherein the first pad is a bonding pad for connecting a metal plate, and   wherein the second pad is a bonding pad for connecting a wire.   
     
     
         20 . The method of manufacturing a semiconductor device according to  claim 12 ,
 wherein, in the step (e1), the first nickel plated layer and the second nickel plated layer are grown in a state where a concentration of a reducing agent in a plating solution in a vicinity of the portion of the first conductive film pattern exposed in the first opening portion is lower than that in a vicinity of the portion of the second conductive film pattern exposed in the second opening portion.