Interconnect structure and method of forming the same
Abstract
Aspects of the present disclosure include a semiconductor device which includes a dielectric layer deposited over a conductive region and an interconnect electrically connecting the conductive region with a top surface of the dielectric layer. The interconnect includes a barrier layer extending from an interior of the dielectric layer to the conductive region and covering the conductive region. The barrier layer encases a cobalt plug. The interconnect includes a tungsten cap on an upper surface of the cobalt plug. The tungsten cap is coplanar with an upper surface of the dielectric layer. A method of manufacturing the semiconductor device is also provided.
Claims
exact text as granted — not AI-modified1 - 12 . (canceled)
13 . A semiconductor device comprising:
a dielectric layer deposited over a conductive region; an interconnect electrically connecting the conductive region to a plane defined by a top surface of the dielectric layer, the interconnect comprising:
a barrier layer covering the conductive region, the barrier layer encasing a cobalt plug, a tungsten cap on an upper surface of the cobalt plug, the tungsten cap coplanar with the top surface of the dielectric layer, wherein the tungsten cap comprises a first layer positioned on the cobalt plug and adjacent to sidewalls of the dielectric layer, and a second layer positioned within the first layer, wherein an upper surface of the first layer is coplanar with an upper surface of the second layer and the top surface of the dielectric layer.
14 . (canceled)
15 . The semiconductor device according to claim 13 , further comprising a fluorine free tungsten interlayer between the barrier layer and the cobalt plug.
16 . The semiconductor device according to claim 13 , wherein the barrier layer comprises titanium nitride.
17 . The semiconductor device according to claim 13 , wherein the barrier layer comprises a dual layer of titanium deposited on titanium nitride.
18 . The semiconductor device according to claim 13 , wherein the barrier layer comprises titanium.
19 . The semiconductor device according to claim 13 , wherein the conductive region comprises silicide.
20 . The semiconductor device according to claim 13 , further comprising a titanium liner between the conductive region and the barrier layer.Join the waitlist — get patent alerts
Track US2018138123A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.