US2018138121A1PendingUtilityA1

Semiconductor device and a method of increasing a resistance value of an electric fuse

Assignee: RENESAS ELECTRONICS CORPPriority: Mar 7, 2006Filed: Jan 12, 2018Published: May 17, 2018
Est. expiryMar 7, 2026(expired)· nominal 20-yr term from priority
H10W 42/80H10W 20/497H10W 20/49H10W 20/4421H10W 20/435H10W 20/425H10W 20/48H10W 20/43H10W 20/493H01H 85/041H01L 23/5227H01L 23/5256H01L 23/53238H01L 23/53228H01L 23/525H01L 23/5283H01L 2924/0002H01L 23/62H01L 23/528H01L 2924/00H01L 23/5329
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Claims

Abstract

A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.

Claims

exact text as granted — not AI-modified
We claim: 
     
         1 . A semiconductor device, comprising:
 a semiconductor substrate;   an interlayer dielectric formed on the semiconductor substrate;   a first insulating layer formed on the interlayer dielectric, and having a first trench;   a barrier film formed on side and bottom surfaces of the first trench;   an electric fuse formed on the barrier film in the first trench;   a second insulating layer formed on the electric fuse and on the first insulating layer such that the second insulating layer directly contacts with the electric fuse; and   a third insulating layer formed on the second insulating layer,   wherein a linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and   wherein a melting point of the barrier film is greater than a melting point of the electric fuse.   
     
     
         2 . The semiconductor device according to the  claim 1 , wherein the electric fuse includes copper. 
     
     
         3 . The semiconductor device according to the  claim 1 , further comprising a first wiring formed in a second trench formed in the first insulating layer,
 wherein a width of the electric fuse is smaller than a width of the first wiring.   
     
     
         4 . The semiconductor device according to the  claim 3 , wherein the electric fuse is comprised of a second wiring having both ends connected with the first wiring. 
     
     
         5 . The semiconductor device according to the  claim 1 ,
 wherein the second insulating layer includes first and second layers,   wherein the first layer includes Si and O, and   wherein the second layer includes Si, C and N.   
     
     
         6 . The semiconductor device according to the  claim 1 , wherein the first insulating layer has a relative dielectric constant of 3 or less. 
     
     
         7 . The semiconductor device according to the  claim 1 , further comprising;
 a fourth insulating layer formed on the third insulating layer, and having a third trench; and   a third wiring formed in the third trench,   wherein a width of the third wiring is greater than a width of the first wiring.   
     
     
         8 . The semiconductor device according to the  claim 1 , wherein the electric fuse is formed to be cut by applying an electrical current to the electric fuse. 
     
     
         9 . The semiconductor device according to  claim 1 , wherein the barrier film includes Ta. 
     
     
         10 . The semiconductor device according to  claim 2 , wherein the barrier film is located between the copper film and the side and bottom surfaces of the first trench. 
     
     
         11 . The semiconductor device according to  claim 1 , wherein the barrier film includes first and second barrier films at the side surface of the first trench. 
     
     
         12 . The semiconductor device according to  claim 11 , wherein the first barrier film includes Ta and the second barrier film includes TaN.

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