Power field-effect transistor (fet), pre-driver, controller, and sense resistor integration for multi-phase power applications

Abstract

Techniques are described for integrating power field-effect transistors (FETs), pre-drivers, controllers, and/or resistors into a common multi-chip package for implementing multi-phase bridge circuits. The techniques may provide a multi-chip package with at least two high-side (HS) FETs and at least two low-side (LS) FETs, and place the at least two HS FETs or the at least LS FETs on a common die. Placing at least two FETs on a common die may reduce the number of die and the number of thermal pads (i.e., die pads) needed to implement a set of power FETs, thereby decreasing component count of a multi-phase bridge circuit and/or allowing a more compact, higher current density multi-phase bridge circuit to be obtained without significantly increasing thermal power dissipation of the circuit.

What is claimed is: 
     
         1 . A multi-chip package comprising:
 at least two low-side (LS) field-effect transistors (FETs);   at least two high-side (HS) FETs; and   a die including the at least two HS FETs or the at least two LS FETs.   
     
     
         2 . The multi-chip package of  claim 1 ,
 wherein the die is a first die that includes the at least two HS FETs, wherein the multi-chip package further comprises:   a second die that includes a first LS FET of the at least two LS FETs; and   a third die that includes a second LS FET of the at least two LS FETs.   
     
     
         3 . The multi-chip package of  claim 2 , further comprising:
 a fourth die that includes at least one of a controller circuit or a driver circuit.   
     
     
         4 . The multi-chip package of  claim 3 , further comprising:
 a first resistor coupled to a source electrode of the first LS FET; and   a second resistor coupled to a source electrode of the second LS FET.   
     
     
         5 . The multi-chip package of  claim 1 , wherein the die is a first die that includes the at least two HS FETs, wherein the multi-chip package further comprises:
 a second die that that includes at least one of the two LS FETs.   
     
     
         6 . The multi-chip package of  claim 5 , further comprising:
 a thermal pad;   a third die that includes at least one of a controller circuit or a driver circuit;   wherein the second die and the third die are disposed on the thermal pad.   
     
     
         7 . The multi-chip package of  claim 6 , wherein the second die includes at least two of the LS FETS. 
     
     
         8 . The multi-chip package of  claim 6 , wherein the at least two HS FETs are drain substrate HS FETs, and wherein the at least two LS FETs are source substrate LS FETs. 
     
     
         9 . The multi-chip package of  claim 1 , wherein the die is a first die that includes the at least two HS FETs, and wherein the at least two HS FETs are drain substrate HS FETs. 
     
     
         10 . The multi-chip package of  claim 1 , wherein the die is a first die that includes the at least two LS FETs, and wherein the multi-chip package further comprises:
 a second die that includes a first HS FET of the at least two HS FETs; and   a third die that includes a second HS FET of the at least two HS FETs, wherein the second and third dies are vertically-stacked on top of the first die.   
     
     
         11 . The multi-chip package of  claim 10 , further comprising:
 a first clip positioned between the first die and the second die and coupled to a drain electrode of the a first LS FET of the at least two LS FETs, and to a source electrode of the first HS FET; and   a second clip positioned between the first die and the third die and coupled to a drain electrode of the a second LS FET of the at least two LS FETs, and to a source electrode of the second HS FET.   
     
     
         12 . The multi-chip package of  claim 10 , further comprising:
 a fourth die that includes at least one of a controller circuit or a driver circuit.   
     
     
         13 . The multi-chip package of  claim 10 , further comprising:
 a first resistor coupled to a drain electrode of the first HS FET; and   a second resistor coupled to a drain electrode of the second HS FET.   
     
     
         14 . The multi-chip package of  claim 1 , wherein the die is a first die that includes the at least two LS FETs, wherein the multi-chip package further comprises:
 a second die that includes the at least two HS FETs, wherein the second die is vertically-stacked on top of the first die.   
     
     
         15 . The multi-chip package of  claim 14 , further comprising:
 a third die that includes at least one of a controller circuit or a driver circuit.   
     
     
         16 . The multi-chip package of  claim 14 , further comprising:
 a resistor coupled to a drain electrode of the first and second HS FETs.   
     
     
         17 . The multi-chip package of  claim 1 , wherein the die is a first die that includes the at least two LS FETs, wherein the multi-chip package further comprises:
 a thermal pad;   a second die that includes at least one of the least two HS FETs, wherein the second die is vertically-stacked on top of the first die; and   a third die that includes at least one of a controller circuit or a driver circuit,   wherein the first die and the third die are disposed on the thermal pad.   
     
     
         18 . The multi-chip package of  claim 17 , wherein the second die includes the at least two HS FETs. 
     
     
         19 . A multi-chip package comprising:
 at least two low-side (LS) field-effect transistors (FETs);   at least two high-side (HS) FETs;   a first die including the at least two HS FETs or the at least two LS FETs; and   a second die including at least one of a controller circuit or a driver circuit.   
     
     
         20 . A multi-chip package comprising:
 at least two low-side (LS) field-effect transistors (FETs);   at least two high-side (HS) FETs;   a first die including the at least two HS FETs or the at least two LS FETs;   a second die including at least one of a controller circuit or a driver circuit; and   a first resistor coupled to a first one of the at least two HS FETs or the at least two LS FETs; and   a second resistor coupled to a second one of the at least two HS FETs or the at least two LS FETs.