Vertical system integration

Abstract

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

1 .- 20 . (canceled) 
     
     
         21 . A method of making a stacked integrated circuit, comprising:
 stacking a plurality of closely-coupled integrated circuit layers in relation to one another; and   interconnecting at least two of the plurality of closely-coupled integrated circuit layers using a plurality of vertical interconnections in a standardized placement, wherein the plurality of closely-coupled integrated circuit layers comprise at least a logic layer and a memory layer that have a same standardized placement interconnection pattern as corresponding logic layer and memory layer integrated circuit layers of at least one different stacked integrated circuit having a different design than said stacked integrated circuit;   wherein a unique integrated circuit layer is present in only one of the stack of integrated circuits and the different stacked integrated circuit, and wherein the unique integrated circuit layer, the stacked integrated circuit and the different stacked integrated circuit share a same standardized placement interconnection pattern.   
     
     
         22 . The method of  claim 21 , wherein, in said stacking step, the closely-coupled integrated circuit layers comprise first stacked integrated circuit layers that are instances of a set of designs of different mutually interchangeable stacked integrated circuit layers, the first stacked integrated circuit layers consisting of a first subset of the set of designs of different mutually interchangeable stacked integrated circuit layers, and the at least one different stacked integrated circuit comprising second stacked integrated circuit layers that are instances of the same set of designs of different mutually interchangeable stacked integrated circuit layers, the second stacked integrated circuit layers consisting of a second subset of the set of designs of different mutually interchangeable stacked integrated circuit layers, wherein at least one of:
 the first subset is different than the second subset;   the first subset is the same as the second subset, and each of the stacked integrated circuit and the at least one different stacked integrated circuit comprises at least a plural number N of stacked integrated circuit layers, but for at least one number N, an Nth stacked integrated circuit layer counting from a bottom-most layer of the stacked integrated circuit and an Nth stacked integrated circuit layer counting from a bottom-most layer of the at least one different stacked integrated circuit are instances of different designs of the set of designs of different mutually interchangeable stacked integrated circuit layers.   
     
     
         23 . The method of  claim 21 , wherein, in said stacking step, the closely-coupled integrated circuit layers comprise stacked integrated circuit layers that are instances of a first subset of a set of designs of different mutually interchangeable stacked integrated circuit layers, and the at least one different stacked integrated circuit comprises stacked integrated circuit layers that are instances of a second subset of the set of designs of different mutually interchangeable stacked integrated circuit layers, wherein the first subset is different than the second subset. 
     
     
         24 . The method of  claim 21 , wherein, in said stacking step, the closely-coupled integrated circuit layers comprise first stacked integrated circuit layers that are instances of a first subset of a set of designs of different mutually interchangeable stacked integrated circuit layers, and wherein the at least one different stacked integrated circuit comprises second stacked integrated circuit layers that are instances of a second subset of the set of designs of different mutually interchangeable stacked integrated circuit layers, wherein the first subset is the same as the second subset, and each of the stacked integrated circuit and the at least one different stacked integrated circuit comprises at least a plural number N of stacked integrated circuit layers, but for at least one number N, an Nth stacked integrated circuit layer counting from a bottom-most layer of the stacked integrated circuit and an Nth stacked integrated circuit layer counting from a bottom-most layer of the at least one different stacked integrated circuit are instances of different designs of the set of designs of different mutually interchangeable stacked integrated circuit layers. 
     
     
         25 . The method of  claim 21 , wherein, in said stacking step, at least one of the closely-coupled integrated circuit layers comprises stress balanced dielectrics.