Vertical system integration

Abstract

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

What is claimed is: 
     
         1 . A method of making a stacked integrated circuit comprising:
 stacking a plurality of closely coupled integrated circuit layers; and   fine grain vertical interconnections interconnecting the plurality of closely coupled integrated circuit layers using fine grain vertical interconnections;   wherein physical footprint sizes and placement of the fine grain vertical interconnections is standardized among a plurality of integrated circuit implementations.   
     
     
         2 . The method of  claim 1 , comprising:
 making a design change to one of the plurality of closely coupled integrated circuit layers, requiring it to be fabricated to reflect the design change; and   making a derivative stacked integratred circuit using the one of the plurality of closely coupled integrated circuit layers and one of the other plurality of closely coupled integrated circuit layers, without the one of the other plurality of closely coupled integrated circuit layers to be refabricated as a consequence of the design change.   
     
     
         3 . A method of making a stacked integrated circuit comprising:
 stacking a plurality of closely coupled integrated circuit layers; and   fine grain vertical interconnections interconnecting the plurality of closely coupled integrated circuit layers using fine grain vertical interconnections;   wherein physical footprint sizes and placement of the fine grain vertical interconnections is standardized among a plurality of integrated circuit implementations, and wherein the area of the total surface area of the plurality of closely coupled integrated circuit layers is greater than the surface area of the largest single layer integrated circuit that can be made.   
     
     
         4 . A method of making a stacked integrated circuit comprising:
 stacking a plurality of closely coupled integrated circuit layers; and   fine grain vertical interconnections interconnecting the plurality of closely coupled integrated circuit layers using fine grain vertical interconnections;   wherein physical footprint sizes and placement of the fine grain vertical interconnections is standardized among a plurality of integrated circuit implementations, and wherein the surface areas of at least one of the plurality of closely coupled integrated circuit layers is determined by its design and not by a required amount of circuitry.   
     
     
         5 . A method of making a stacked integrated circuit comprising:
 stacking a plurality of closely coupled integrated circuit layers; and   fine grain vertical interconnections interconnecting the plurality of closely coupled integrated circuit layers using fine grain vertical interconnections;   wherein physical footprint sizes and placement of the fine grain vertical interconnections is standardized among a plurality of integrated circuit implementations, and wherein the surface areas of the plurality of closely coupled integrated circuit layers are independent of a required amount of circuitry of the stacked integrated circuit.   
     
     
         6 . The method of  claim 3 , wherein the surface area of the largest single layer integrated circuit is less than 25×30 mm.