US2018130905A1PendingUtilityA1

Semiconductor device and method for fabricating the same

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Nov 7, 2016Filed: Jun 12, 2017Published: May 10, 2018
Est. expiryNov 7, 2036(~10.3 yrs left)· nominal 20-yr term from priority
H10P 95/90H10P 14/40H01L 21/283H01L 29/42356H01L 29/66666H01L 21/324H01L 29/0676H01L 29/511H01L 29/7831H01L 29/7827H01L 29/66484H10D 30/798H10D 64/017H10D 62/213H10D 30/611H10D 64/685H10D 64/681H10D 64/514H10D 64/512H10D 62/122H10D 62/121H10D 62/116H10D 30/6757H10D 30/6739H10D 30/6735H10D 30/63H10D 30/43H10D 30/025H10D 30/023H10D 30/014B82Y 10/00
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Claims

Abstract

A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device comprising:
 first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent to a first channel region and the second gate stack structure is formed adjacent to a second channel region,   wherein the first gate stack structure comprises:   a first gate insulating film having a first thickness formed on the first channel region;   a first function film having a second thickness formed on the first gate insulating film; and   a first filling film having a third thickness formed on the first function film;   wherein the second gate stack structure comprises:   a second gate insulating film having the first thickness formed on the second channel region;   a second function film having the second thickness formed on the second gate insulating film; and   a second filling film having the third thickness formed on the second function film,   wherein the first and second function films comprise TiN, and wherein Si concentrations of the first and second function films are different from each other.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first and second function films are a single film. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first function film comprises a first interfacial function film and a first barrier function film alternately stacked, and
 wherein the second function film comprises a second interfacial function film and a second barrier function film alternately stacked.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the first and second interfacial function films comprise TIN, and
 wherein the first and second barrier function films comprise Si.   
     
     
         5 . The semiconductor device of  claim 3 , wherein a ratio of the thickness of the first barrier function film relative to the thickness of the first interfacial function film, and
 wherein a ratio of the thickness of the second barrier function film relative to the thickness of the second interfacial function film are different from each other.   
     
     
         6 . The semiconductor device of  claim 3 , wherein the first and second interfacial function films comprise amorphous TIN, and
 wherein the first and second barrier function films comprise crystalline Si   
     
     
         7 . The semiconductor device of  claim 1 , wherein the first and second channel regions comprise Si. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the first gate insulating film comprises a first interfacial layer and a first high-k film on the first interfacial layer,
 wherein the second gate insulating film comprises a second interfacial layer and a second high-k film on the second interfacial layer, and   wherein the first and second high-k films have a higher dielectric constant than a silicon oxide film.   
     
     
         9 . The semiconductor device of  claim 1 ,
 wherein the first function film comprises TiSiN, and   wherein the second function film comprises TiN but not Si.   
     
     
         10 . A semiconductor device, comprising:
 a substrate comprising first and second regions;   first and second channel regions formed in the first and second regions, respectively;   first and second gate insulating films formed on the first and the second channel regions, respectively;   first and second function films formed on the first and second gate insulating films, respectively, and wherein a Si concentration of the first function film and a Si concentration of the second function film are different from each other; and   first and second filling films formed on the first and the second function films, respectively,   wherein the first and second function films are a TiSiN single film, or multiple films including a TiN film and a Si film alternately stacked.   
     
     
         11 . The semiconductor device of  claim 10 ,
 wherein the first and second channel regions are first and second nanowires spaced apart from the substrate, respectively,   wherein the first gate insulating film, the first function film, and the first filling film surround the first nanowire, and   wherein the second gate insulating film, the second function film, and the second filling film surround the second nanowire.   
     
     
         12 . The semiconductor device of  claim 11 , further comprising:
 a first source/drain connecting with the first channel region on opposite sides of the first channel region, and   a second source/drain connecting with the second channel region on opposite sides of the second channel region.   
     
     
         13 . The semiconductor device of  claim 12 ,
 wherein the first and the second channel regions extend in a horizontal direction,   wherein the first source/drain is in contact with an upper surface and a bottom surface of the first channel region, respectively, and   wherein the second source/drain is in contact with an upper surface and a bottom surface of the second channel region, respectively.   
     
     
         14 . The semiconductor device of  claim 10 ,
 wherein the substrate comprises:   a first fin protruding in the first region and extending in a first direction; and   a second fin protruding in the second region and extending in a second direction, and   wherein the first and second channel regions are on upper portions of the first and second fins, respectively.   
     
     
         15 . The semiconductor device of  claim 14 , further comprising:
 a first recess formed on either side of the first channel region, within the first fin;   a first source/drain formed in the first recess;   a second recess formed on either side of the second channel region, within the second fin; and   a second source/drain formed in the second recess.   
     
     
         16 . A method manufacturing a semiconductor device, comprising:
 forming a first gate insulating film on a first channel region in a first region;   forming above the first gate insulating film a first Ti film and a first N film;   forming a second gate insulating film on a second channel in a second region adjacent to the first region;   forming above the second gate insulating film a second Ti film and a second N film,   wherein each of the first and second gate insulating films have a first thickness H 1 , a a first combination of the first Ti film and the first N film have a second thickness H 2 , and a second combination of the second Ti film and the second N film have the second thickness H 2 ,   performing a heat treatment in first and second regions to cause the first Ti film and the first N film to become a first function film and the second Ti film and the second N film to become a second function film;   performing a first doping in the first region and a second doping in the second region, wherein both the first doping and the second doping are Si doping; and   forming a first filling film and a second filling film, respectively, on said first and second function films.   
     
     
         17 . The method of  claim 16 , wherein the first and second N films directly contact, respectively, the first and second gate insulating films. 
     
     
         18 . The method of  claim 16 , wherein the first and second Ti films directly contact, respectively, the first and second gate insulating films. 
     
     
         19 . The method of  claim 16 , wherein the amount of Si doping in the second doping is greater than the amount of Si doping in first doping. 
     
     
         20 . The method of  claim 16 , wherein concentrations of Si in the first and second function films are different from each other.

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