Method for refreshing memory cells and memory system

Abstract

A method for refreshing memory cells includes: reading data from a plurality of memory cells; and performing a write operation with a first data onto memory cells from which the first data is read among the plurality of memory cells.

What is claimed is: 
     
         1 . A method for refreshing memory cells, comprising:
 reading data from a plurality of memory cells; and   performing a write operation with a first data onto memory cells from which the first data is read among the plurality of memory cells.   
     
     
         2 . The method of  claim 1 , wherein each of the plurality of memory cells includes:
 a resistive memory element; and   a selection element.   
     
     
         3 . The method of  claim 2 , wherein the resistive memory element is a phase-change memory element. 
     
     
         4 . The method of  claim 3 , wherein the selection element is an Ovonic Threshold Switch (OTS). 
     
     
         5 . A method for refreshing memory cells, comprising:
 reading data from a plurality of memory cells;   detecting and correcting an error data of the read data into an error-corrected data;   deciding to perform a write operation onto memory cells from which a first data is read among the plurality of memory cells and deciding to perform the write operation onto a memory cell from which the error data is detected among the plurality of memory cells; and   performing the write operation onto memo cells that the write operation is decided to be performed.   
     
     
         6 . The method of  claim 5  wherein in the performing of the write operation onto the memory cells that the write operation is decided to be performed,
 a corrected data is written in the memory cell from which the error bit is read, and the first data is written in the memory cells other than the memory cell from which the error bit is read. 
 
     
     
         7 . The method of  claim 5 , wherein each of he plurality of memory cells includes:
 a resistive memory element; and   a selection element.   
     
     
         8 . The method of  claim 7 , wherein the resistive memory element is a phase-change memory element. 
     
     
         9 . The method of  claim 8 , wherein the selection device is an Ovonic Threshold Switch OTS). 
     
     
         10 . A memory system, comprising:
 a resistive memory device; and   a memory controller suitable for controlling the resistive memory device,   wherein, during a refresh operation of the resistive memory device, the memory controller reads data from a plurality of memory cells and performs a write operation with a first data onto memory cells from which the first data is read among the plurality of memory cells.   
     
     
         11 . The memory system of  claim 10 , wherein the memory controller performs the write operation with the first data by writing the read data into the plurality of memory cells while masking memory cells storing data other than the first data among the plurality of memory cells. 
     
     
         12 . The memory system of  claim 10 , wherein each of the plurality of memory cells includes:
 a resistive memory element; and   a selection element.   
     
     
         13 . The memory system of  claim 12 ,
 wherein the resistive memory device is a phase-change memory element, and   wherein the selection device is an Ovonic Threshold Switch (OTS).   
     
     
         14 . A memory system, comprising:
 a resistive memory device; and   a memory controller suitable for controlling the resistive memory device,   wherein, during a refresh operation of the resistive memory device, the memory controller reads data from a plurality of memory cells, detects and corrects an error data of the read data into an error-corrected data, performs a write operation onto memory cells from which a first data is read and onto a memory cell from which the error data is read   
     
     
         15 . The memory system of  claim 14 , wherein, during the write operation,
 the error-corrected data is written in the memory cell from which the error data is read, and the first data is written in the memory cells other than the memory cell from which the error bit is read.   
     
     
         16 . The memory system of  claim 15 , wherein the memory controller performs the write operation with the first data and the error-corrected data by writing the read data, which is error-corrected, into the plurality of memory cells while masking memory cells storing data other than the first data and the error data among the plurality of memory cells. 
     
     
         17 . The memory system of  claim 14 , wherein each of the plurality of memory cells includes:
 a resistive memory element; and   a selection element.   
     
     
         18 . The memory system of  claim 17 ,
 wherein the resistive memory element is a phase-change memory element, and   wherein the selection device is an Ovonic Threshold Switch (OTS).