Voltage control circuit for providing two voltages generated based on a parameter corresponding to an input signal

Abstract

Disclosed is a nonvolatile storage system including: a memory block having a plurality of flash memories; a flash memory power supply circuit outside of the memory block; and a flash memory controller. The flash memory power supply circuit has a plurality of types of power supply circuits for process execution, the power supply circuits for process execution generating and supplying power at a plurality of voltage levels needed to execute processes in the flash memories. The flash memory controller monitors changes of the internal states of the flash memories by communicating with the flash memories, thereby controlling the power supply circuits for process execution and the flash memories.

1 . A non-volatile semiconductor storage device, comprising:
 a memory cell array having a plurality of flash memories;   a first terminal for inputting data to be written in the plurality of memory cells and outputting data read from the plurality of memory cells;   a command register that receives a command for designating an operating state of the memory;   a controller configured to control an internal operational sequence based on a value of the command register; and   a second terminal for outputting a signal indicating an internal operating state generated by the controller.   
     
     
         2 . The non-volatile semiconductor storage device as claimed in  claim 1 , further comprising a register that stores the internal operating state generated by the controller, wherein
 the second terminal is a terminal for outputting data stored by the register.   
     
     
         3 . The non-volatile semiconductor storage device as claimed in  claim 1 , further comprising a terminal for outputting a signal that broadcasts any change of the internal operating state generated by the controller. 
     
     
         4 . The non-volatile semiconductor storage device as claimed in  claim 1 , further comprising a terminal for receiving a signal that controls progression of the internal operational sequence. 
     
     
         5 . The non-volatile semiconductor storage device as claimed in  claim 1 , further comprising:
 a first power supply terminal to which a first power supply voltage to be applied to a logic circuit is applied; and   a second power supply terminal to which a second power supply voltage higher than the first power supply voltage is applied.   
     
     
         6 . The non-volatile semiconductor storage device as claimed in  claim 5 , further comprising a third power supply terminal to which a third power supply voltage higher than the second power supply voltage is applied. 
     
     
         7 . The non-volatile semiconductor storage device as claimed in  claim 1 , wherein the second terminal and the first terminal are a common terminal. 
     
     
         8 . The non-volatile semiconductor storage device as claimed in  claim 1 , wherein the second terminal is a terminal that is distinct from the first terminal. 
     
     
         9 . The non-volatile semiconductor storage device as claimed in  claim 1 , wherein the signal indicating the internal operating state comprises at least information indicating data reading, programs, and status of erasure. 
     
     
         10 . The non-volatile semiconductor storage device as claimed in  claim 1 , wherein the signal indicating the internal operating state comprises a least information indicating data reading, programs, program verification, erasure, and status of erasure verification. 
     
     
         11 . The non-volatile semiconductor storage device as claimed in  claim 9 , wherein the signal indicating the internal operating state comprises operation parameters associated with programs and operations. 
     
     
         12 . The non-volatile semiconductor storage device as claimed in  claim 11 , wherein the operation parameters comprise number of verifications, an operation voltage level, and an applied voltage pulse width. 
     
     
         13 . A non-volatile semiconductor storage device, comprising:
 a memory cell array having a plurality of flash memories;   a first terminal for inputting data to be written in the plurality of memory cells and for outputting data read from the plurality of memory cells;   a non-volatile storage region that stores chip-specific information; and a second terminal for outputting the chip-specific information stored in the non-volatile storage region.   
     
     
         14 . The non-volatile semiconductor storage device as claimed in  claim 13 , further comprising:
 a command register that receives a command for designating an operating state of the memory cell array;   a controller configured to control an internal operational sequence in accordance with a value of the command register;   a register that stores a signal indicating an internal operating state generated by the controller and that transfers the chip-specific information stored in the non-volatile storage region.   
     
     
         15 . The non-volatile semiconductor storage device as claimed in  claim 13 , further comprising:
 a first power supply terminal to which a first power supply voltage to be applied to a logic circuit is applied; and   a second power supply terminal to which a second power supply voltage higher than the first power supply voltage is applied.   
     
     
         16 . The non-volatile semiconductor storage device as claimed in  claim 15 , further comprising a third power supply terminal to which a third power supply voltage higher than the second power supply voltage is applied. 
     
     
         17 . The non-volatile semiconductor storage device as claimed in  claim 13 , wherein the second terminal and the first terminal are a common terminal. 
     
     
         18 . The non-volatile semiconductor storage device as claimed in  claim 13 , wherein the second terminal is a terminal that is distinct from the first terminal. 
     
     
         19 . A flash memory controlled to operate by a flash memory controller externally provided, the flash memory comprising:
 a register that indicates a level of power consumed by the flash memory in a respective one of operation modes of the flash memory; and   a controller configured to broadcasts the level of power indicated by the register to the flash memory controller.   
     
     
         20 . The flash memory as claimed in  claim 19 , wherein the controller transmits and receives a command that includes a field indicating the level of power to and from the flash memory controller. 
     
     
         21 . The flash memory as claimed in  claim 19 , wherein the operation modes include an operation stoppage mode. 
     
     
         22 . The flash memory as claimed in  claim 21 , further comprising a control terminal for designating a level of power during the operation stoppage mode. 
     
     
         23 . The flash memory as claimed in  claim 21 , wherein the controller allows an access to the register when the flash memory is operating during the operation stoppage mode. 
     
     
         24 . The flash memory as claimed in  claim 19 , further comprising a first storage that stores a first piece of information indicating a value of operating power consumed by the flash memory at a respective one of the level of power, wherein
 the controller reads the first piece of information corresponding to the level of power from the first storage and supplies the flash memory controller with the first piece of information.   
     
     
         25 . The flash memory as claimed in  claim 19 , further comprising a second storage that stores a second piece of information indicating a processing speed of the flash memory at a respective one of the level of power, wherein
 the controller reads the second piece of information corresponding to the level of power from the second storage and supplies the flash memory controller with the second piece of information.   
     
     
         26 . The flash memory as claimed in  claim 19 , wherein the controller relies on a signal inputted from outside to the flash memory, instead of the level of power indicated by the register, to grasp the level of power. 
     
     
         27 . The flash memory as claimed in  claim 19 , wherein electric current consumed by the flash memory changes when the register indicating the level of power is overwritten by the flash memory controller.