Systems and method involving fast-acquisition lock features associated with phase locked loop circuitry

Abstract

Systems and methods are disclosed relating to fields of clock/data acquisition or handling, such as clock/data locking and the like. In one exemplary implementation, phase lock loop (PLL) circuitry may comprise voltage controlled oscillator (VCO) circuitry, phase frequency detector, converting circuitry, and frequency detector (FD) circuitry that outputs a frequency difference signal proportional to frequency difference between frequencies of a feedback clock signal and a reference clock signal.

1 . Phase lock loop (PLL) circuitry comprising:
 voltage controlled oscillator (VCO) circuitry that generates a feedback clock signal;   phase frequency detector (PFD) circuitry that receives the feedback clock signal and a reference clock signal, compares phase of the feedback clock signal to phase of the reference clock signal, and outputs a phase comparison signal;   frequency detector (FD) circuitry that receives the feedback clock signal and the reference clock signal, compares frequency of the feedback clock signal to frequency of the reference clock signal, and outputs a frequency difference signal that is proportional to frequency difference between frequencies of the feedback clock signal and the reference clock signal determined by the comparison;   bit-wise logic operation and register circuitry that latches a state of a first shift register chain circuitry and a state of a second shift register chain circuitry;   converting circuitry that receives the phase comparison signal and/or the frequency difference signal and outputs, to the VCO circuitry, a control signal proportional to the phase comparison signal and/or the frequency difference signal.   
     
     
         2 . The circuitry of  claim 1 , wherein the frequency detector circuitry further comprises:
 first shift register chain circuitry that receives the reference clock signal; second shift register chain circuitry that receives the feedback clock signal; and gate circuitry that generates a set signal based on an output of the first shift register chain circuit and/or an output of the second shift register chain circuitry;   wherein the frequency detector circuitry receives a feedback clock signal and a reference clock signal, compares frequency of the feedback clock signal to frequency of the reference clock signal, and outputs a frequency difference signal that is proportional to frequency difference between frequencies of the feedback clock signal and the reference clock signal determined by the comparison.   
     
     
         3 . A method for operating phase lock loop (PLL) circuitry, the method comprising:
 generating, via voltage controlled oscillator (VCO) circuitry, a feedback clock signal;   receiving, via frequency detector (FD) circuitry, the feedback clock signal and a reference clock signal;   comparing, via the FD circuitry, a frequency of the feedback clock signal to a frequency of the reference clock signal; and   outputting, via the FD circuitry, a frequency difference signal that is proportional to a frequency difference between the frequency of the feedback clock and the frequency of the reference clock signal determined by the comparing of the frequencies.   
     
     
         4 . The method of  claim 3 , wherein the comparing the frequencies is performed as a function of shift register chains within the FD circuitry. 
     
     
         5 . The method of  claim 3  further comprising providing a control signal proportional to the frequency difference signal to the VCO circuitry. 
     
     
         6 . The method of  claim 3 , wherein comparing the frequencies further comprises latching a state of a first shift register chain circuitry and a state of a second shift register chain circuitry via bit-wise logic operation and register circuitry. 
     
     
         7 . The method of  claims 3  further comprising dividing, via first divider circuitry, a primary reference clock signal to output the reference clock signal; and dividing, via second divider circuitry, a primary feedback clock signal to output the feedback clock signal. 
     
     
         8 . A method for operating phase lock loop (PLL) circuitry, the method comprising:
 generating, via voltage controlled oscillator (VCO) circuitry, a feedback clock signal;   receiving, via phase frequency detector (PFD) circuitry, the feedback clock signal and a reference clock signal;   comparing, via the PFD circuitry, a phase of the feedback clock signal to a phase of the reference clock signal;   outputting, via the PFD circuitry, a phase comparison signal; receiving, via first charge pump circuitry, the phase comparison signal; outputting, via the first charge pump circuitry, a control signal proportional to the phase comparison signal to the VCO circuit;   receiving, via frequency detector (FD) circuitry, the feedback clock signal and the reference clock signal;   comparing, via the FD circuitry, a frequency of the feedback clock signal to a frequency of the reference clock signal; and   outputting, via the FD circuitry, a frequency difference signal that is proportional to a frequency difference between the frequency of the feedback clock and the frequency of the reference clock signal determined by the comparing of the frequencies; receiving, via second charge pump circuitry, the frequency difference signal; and outputting, via the second charge pump circuitry, a control signal proportional to the frequency difference signal to the VCO circuit.   
     
     
         9 . The method of  claims 8  further comprising dividing, via first divider circuitry, a primary reference clock signal to output the reference clock signal; and dividing, via second divider circuitry, a primary feedback clock signal to output the feedback clock signal. 
     
     
         10 . The method of  claims 8  further comprising removing, via low pass frequency (LPF) circuitry, one or more high frequency components of one of the control signal output by the first charge pump circuitry and the control signal output by the second charge pump circuitry. 
     
     
         11 . The method of  claim 10  further comprising adjusting, via the LPF circuitry, a loop stability characteristic of the PLL circuitry; adjusting, via the LPF circuitry, a response time of the PLL circuitry; and/or adjusting, via the LPF circuitry, a lock-in time of the PLL circuitry. 
     
     
         12 . The method of  claim 8 , wherein outputting the frequency difference signal further comprises receiving, via first shift register chain circuitry, the reference clock signal; receiving, via second shift register chain circuitry, the feedback clock signal; and generating, via gate circuitry, a set signal based on an output of the first shift register chain circuit and/or an output of the second shift register chain circuit. 
     
     
         13 . The method of  claim 12 , wherein the set signal is one of an active high signal and an active low signal.