Semiconductor package and method of manufacturing the semiconductor package

Abstract

A semiconductor package includes a mold substrate, at least one first semiconductor chip in the mold substrate and including chip pads, wiring bonding pads formed at a first surface of the mold substrate and connected to the chip pads by bonding wires, and a redistribution wiring layer covering the first surface of the mold substrate and including redistribution wirings connected to the wiring bonding wirings.

1 . A semiconductor package, comprising:
 a mold substrate;   at least one first semiconductor chip in the mold substrate, the at least one first semiconductor chip including chip pads;   wiring bonding pads at a first surface of the mold substrate, the wiring bonding pads connected to the chip pads by bonding wires; and   a redistribution wiring layer covering the first surface of the mold substrate, the redistribution wiring layer including redistribution wirings, the redistribution wirings connected to the wiring bonding pads.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the redistribution wiring layer comprises a first insulation layer, which is on the first surface of the mold substrate and includes openings exposing the wiring bonding pads. 
     
     
         3 . The semiconductor package of  claim 2 , wherein at least one first redistribution wiring of the redistribution wirings is on the first insulation layer, and portions of the first redistribution wiring are in contact with the wiring bonding pads through the openings. 
     
     
         4 . The semiconductor package of  claim 1 , wherein the chip pads are on a first surface of the first semiconductor chip, and a second surface of the first semiconductor chip is opposite to the first surface and faces the redistribution wiring layer. 
     
     
         5 . The semiconductor package of  claim 4 , wherein the second surface of the first semiconductor chip is exposed from the first surface of the mold substrate. 
     
     
         6 . The semiconductor package of  claim 1 , further comprising:
 a support member in the mold substrate, at least a portion of the support member being exposed through the first surface of the mold substrate.   
     
     
         7 . The semiconductor package of  claim 1 , further comprising:
 a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip.   
     
     
         8 . The semiconductor package of  claim 1 , further comprising:
 a third semiconductor chip in the mold substrate,   wherein the third semiconductor chip includes a plurality of chip pads on a first surface thereof, and the first surface of the third semiconductor chip faces the redistribution wiring layer, and at least some of the redistribution wirings are electrically connected to the chip pads of the third semiconductor chip.   
     
     
         9 . The semiconductor package of  claim 8 , further comprising:
 bump bonding pads formed in the first surface of the mold substrate, and   conductive bumps connecting the bump bonding pads to the chip pads of the third semiconductor chip.   
     
     
         10 . The semiconductor package of  claim 1 , wherein the bonding wires are bonded to first surfaces of the wiring bonding pads, second surfaces of the wiring bonding pads are opposite to the first surfaces of the wiring bonding pad, and the second surfaces are coplanar with the first surface of the mold substrate. 
     
     
         11 - 30 . (canceled) 
     
     
         31 . A semiconductor package, comprising:
 a redistribution wiring layer including redistribution wirings and fan out type landing pads connected to the redistribution wirings;   at least one first semiconductor chip on the redistribution wiring layer, the at least one first semiconductor chip including a first surface having first chip pads thereon and a second surface facing the redistribution wiring layer;   wiring bonding pads at a first surface of the redistribution wiring layer, the wire bonding pads connected to corresponding ones of the redistribution wirings; and   bonding wires connecting the first chip pads with wiring bonding pads such that the first chip pads are connected to corresponding ones of the fan out type landing pads on a second surface of the redistribution wiring layer, the second surface of the redistribution wiring layer being opposite to the first surface of the redistribution wiring layer.   
     
     
         32 . The semiconductor package of  claim 31 , wherein the wiring bonding pads are one of on or in the redistribution wiring layer. 
     
     
         33 . The semiconductor package of  claim 31 , further comprising:
 a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip.   
     
     
         34 . The semiconductor package of  claim 33 , further comprising:
 a support member being adjacent to the first semiconductor chip and vertically between the plurality of second semiconductor chips and the redistribution wiring layer.   
     
     
         35 . The semiconductor package of  claim 31 , further comprising:
 a second semiconductor chip being horizontally adjacent to the first semiconductor chip.   
     
     
         36 . The semiconductor package of  claim 35 , further comprising:
 the second semiconductor chip including second chip pads on a first surface thereof, the first surface facing the redistribution wiring layer, the second chip pads being electrically in contact with corresponding ones of the redistribution wirings.   
     
     
         37 . The semiconductor package of  claim 36 , further including:
 bump bonding pads electrically connected to the second chip pads via conductive bumps.   
     
     
         38 . The semiconductor package of  claim 31 , wherein the redistribution wiring layer comprises a first insulation layer, the first insulation layer faces the second surface of the first semiconductor chip and includes openings, and the wiring bonding pads are in contact with corresponding ones of the redistribution wirings through the openings.