STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S

Abstract

A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

What is claimed is: 
     
         1 . A memory device comprising:
 a memory die wherein the memory die comprises a first through silicon via (TSV), wherein the memory die has a side, wherein the side of the memory die comprises a first electrical connection region and the first electrical connection region is coupled to the first through silicon via (TSV), and   an interface region on the side of the memory die wherein the interface region comprises a first interconnect, wherein the first interconnect is electrically coupled to the first electrical connection region, wherein the first interconnect terminates in a second electrical connection region, and   wherein the first through silicon via (TSV) passes through the memory die in a first direction, wherein the first interconnect provides a first off-set between the first electrical connection region and the second electrical connection region in a second direction, and wherein the first direction is different from the second direction.   
     
     
         2 . The memory device of  claim 1  also including a system element wherein the system element is coupled to the memory die through the interface region. 
     
     
         3 . The memory device of  claim 2  wherein the system element is a system on a chip (SoC). 
     
     
         4 . The memory device of  claim 1  wherein the memory die also comprises a second through silicon via (TSV), wherein the side of the memory die also comprises a third electrical connection region, wherein the third electrical connection region is coupled to the second through silicon via (TSV), wherein the interface region also comprises a second interconnect, wherein the second interconnect is electrically coupled to the third electrical connection region, wherein the second interconnect terminates in a fourth electrical connection region, wherein the second interconnect provides a second off-set between the third electrical connection region and the fourth electrical connection region in a third direction, and wherein the third direction is different from the first direction. 
     
     
         5 . The memory device of  claim 4  wherein the first off-set and the second off-set are the same amount. 
     
     
         6 . The memory device of  claim 4  wherein the first off-set and the second off-set are different amounts. 
     
     
         7 . The memory device of  claim 4  wherein the third direction is different from the second direction. 
     
     
         8 . A memory device comprising:
 a first memory die wherein the first memory die comprises at least two through silicon vias (TSVs), wherein the first memory die has a side, wherein the side of the first memory die has an interface region thereon, wherein the interface region comprises at least two interconnects, and wherein a first interconnect of the at least two interconnects is electrically coupled to a first through silicon via of the at least two through silicon vias (TSVs) and a second interconnect of the at least two interconnects is electrically coupled to a second through silicon via of the at least two through silicon vias (TSVs), and   a second memory die, wherein the second memory die has a side, wherein the side of the second memory die comprises at least two electrical connection regions, and   wherein the first memory die is stacked on the second memory die, wherein the first interconnect of the at least two interconnects is coupled to a first electrical connection region of the at least two electrical connection regions of the second memory die, wherein the first through silicon via (TSV) passes through the first memory die in a first direction, wherein the first interconnect provides an off-set between the first electrical connection region of the second memory die and the first through silicon via (TSV) in a second direction, and wherein the first direction is different from the second direction, and wherein the second interconnect of the at least two interconnects is coupled to a second electrical connection region of the at least two electrical connection regions of the second memory die.   
     
     
         9 . The memory device of  claim 8  wherein the second memory die also comprises at least two through silicon vias (TSVs) and wherein the at least two electrical connection regions of the second memory die are each electrically coupled to a different through silicon via (TSV) of the at least two through silicon vias (TSVs) of the second memory die. 
     
     
         10 . The memory device of  claim 8  also including a third memory die wherein the third memory die is stacked on the first memory die. 
     
     
         11 . The memory device of  claim 9  also including a system element wherein the system element is coupled to the second memory die and is able to communicate with the first memory die through a through silicon via (TSV) of the second memory die. 
     
     
         12 . The memory device of  claim 11  wherein the system element is a system on a chip (SoC). 
     
     
         13 . The memory device of  claim 8  wherein the second through silicon via (TSV) of the at least two through silicon vias (TSVs) lies along a third line, wherein the second interconnect lies along a fourth line, and wherein the third line is different from the fourth line. 
     
     
         14 . The memory device of  claim 10  wherein a bandwidth of the memory device with three dies is larger than a bandwidth of a memory device with two dies. 
     
     
         15 . A system comprising:
 a processor,   a wireless connectivity component wherein the wireless connectivity component allows the system to communicate wirelessly with an external device and wherein the processor and the wireless connectivity component are coupled, and   a memory device wherein the processor and the memory device are coupled and the memory device comprises:   a first memory die wherein the first memory die comprises at least two through silicon vias (TSVs), wherein the first memory die has a side, wherein the side of the first memory die has an interface region thereon, wherein the interface region comprises at least two interconnects, and wherein a first interconnect of the at least two interconnects is electrically coupled to a first through silicon via of the at least two through silicon vias (TSVs) and a second interconnect of the at least two interconnects is electrically coupled to a second through silicon via of the at least two through silicon vias (TSVs), and   a second memory die, wherein the second memory die has a side, wherein the side of the second memory die comprises at least two electrical connection regions, and   wherein the first memory die is stacked on the second memory die, wherein the first interconnect of the at least two interconnects is coupled to a first electrical connection region of the at least two electrical connection regions of the second memory die, wherein the first through silicon via (TSV) passes through the first memory die in a first direction, wherein the first interconnect provides an off-set between the first electrical connection region of the second memory die and the first through silicon via (TSV) in a second direction, and wherein the first direction is different from the second direction, and wherein the second interconnect of the at least two interconnects is coupled to a second electrical connection region of the at least two electrical connection regions of the second memory die.   
     
     
         16 . The system  claim 15  wherein the second memory die also comprises at least two through silicon vias (TSVs) and wherein the at least two electrical connection regions of the second memory die are each electrically coupled to a different through silicon via (TSV) of the at least two through silicon vias (TSVs) of the second memory die. 
     
     
         17 . The system  claim 16  also including a third memory die wherein the third memory die is stacked on the first memory die. 
     
     
         18 . The system  claim 16  also including a system element wherein the system element is coupled to the second memory die and is able to communicate with the first memory die through a through silicon via (TSV) of the second memory die. 
     
     
         19 . The system  claim 18  wherein the system element is a system on a chip (SoC). 
     
     
         20 . The system  claim 16  wherein the second through silicon via (TSV) of the at least two through silicon vias (TSVs) lies along a third line, wherein the second interconnect lies along a fourth line, and wherein the third line is different from the fourth line. 
     
     
         21 . The system  claim 17  wherein a bandwidth of the memory device with three dies is larger than a bandwidth of a memory device with two dies.