Semiconductor device

Abstract

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor chip having an insulating film formed on a first main surface, the insulating film having a first opening exposing a first bonding surface and a second opening exposing a second bonding surface;   a first wire bonded to the first bonding surface of the semiconductor chip;   a second wire bonded to the second bonding surface of the semiconductor chip; and   a sealer that seals the semiconductor chip, the first wire, and the second wire so that the sealer is in contact with the first bonding surface and the second bonding surface of the semiconductor chip,   wherein each of the first bonding surface and the second bonding surface is made of a metal material,   the sealer is made of a resin material,   the first wire includes:
 a first connecting portion bonded to the first bonding surface; 
 a second connecting portion bonded to the first bonding surface; and 
 a first loop portion located between the first connecting portion and the second connecting portion in a first direction in a plan view, the first loop portion being separated from the first bonding surface, 
   the second wire includes:
 a third connecting portion bonded to the second bonding surface; 
 a fourth connecting portion bonded to the second bonding surface; and 
 a second loop portion located between the third connecting portion and the fourth connecting portion in a plan view, the second loop portion being separated from the second bonding surface, 
   in a plan view, the first loop portion includes:
 a fist side extending from the first connecting portion to the second connecting portion in the first direction; and 
 a second side being opposite to the first side, 
   in a plan view, the second loop portion includes:
 a third side extending from the third connecting portion to the fourth connecting portion in the first direction; and 
 a fourth side being opposite to the third side, 
   in a plan view, the first opening and the second opening are arranged in a second direction intersecting the first direction so that the second side of the first loop portion and the third side of the second loop portion are adjacent to each other,   in a plan view, a width of a first region of the insulating film, the first region being sandwiched between the second side of the first wire and the third side of the second wire, is larger than a width of a region sandwiched between the first side and the second side of the first wire, and   each of the width of the first region and the width of the region sandwiched between the first side and the second side of the first wire is defined as a length in the second direction.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the first bonding surface is a first part of a first electrode formed on the first main surface and covered with the insulating film, and   the second bonding surface is a second part of the first electrode formed on the first main surface and covered with the insulating film.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein the first bonding surface is a first part of a first electrode formed on the first main surface and covered with the insulating film, and   the second bonding surface is a first part of a second electrode formed on the first main surface and covered with the insulating film.   
     
     
         4 . The semiconductor device according to  claim 1 ,
 wherein, in the second direction, a width of the third connecting portion of the second wire is smaller than a width of the first region of the insulating film and is different from a width of the first connecting portion of the first wire.   
     
     
         5 . The semiconductor device according to  claim 1 ,
 wherein, in the second direction, a width of the third connecting portion of the second wire is equal to a width of the first connecting portion of the first wire.   
     
     
         6 . The semiconductor device according to  claim 1 ,
 wherein, in the second direction, a maximum width of a region of the first bonding surface, the region being sandwiched between the first wire and the second side of the first bonding surface, is smaller than a width of the first region of the insulating film.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein, in the second direction, a total of a maximum width of a region of the first bonding surface, the region being sandwiched between the first wire and the second side of the first bonding surface, and a maximum width of another region of the first bonding surface, the another region being sandwiched between the first wire and the first side of the first bonding surface, is smaller than a width of the first region of the insulating film.   
     
     
         8 . The semiconductor device according to  claim 1 ,
 wherein, in the second direction, a total of a maximum width of a region sandwiched between the first wire and the second side of the first bonding surface in a region sandwiched between the first wire and the second wire and a maximum width of a region sandwiched between the second wire and the first side of the second bonding surface in the region is smaller than a width of the first region of the insulating film.   
     
     
         9 . The semiconductor device according to  claim 1 ,
 wherein, in the second direction, a maximum width of a region of the first bonding surface, the region being sandwiched between the first wire and the second side of the first bonding surface, is smaller than a width of the first loop portion of the first wire.   
     
     
         10 . The semiconductor device according to  claim 1 ,
 wherein, in the second direction, a total of a maximum width of a region of the first bonding surface, the region being sandwiched between the first wire and the second side of the first bonding surface, and a maximum width of another region of the first bonding surface, the another region being sandwiched between the first wire and the first side of the first bonding surface, is smaller than a width of the first loop portion of the first wire.   
     
     
         11 . A semiconductor device comprising:
 a semiconductor chip including a first main surface formed with an insulating film and a first electrode covered with the insulating film, the first electrode having bonding surfaces exposed from a plurality of openings formed in the insulating film;   a chip mounting portion including a second main surface on which the semiconductor chip is mounted;   a first lead extending from the chip mounting portion and a second lead extending along the first lead;   a plurality of conductive members electrically connecting the second lead to the bonding surfaces of the first electrode, the bonding surfaces being exposed from the plurality of openings, respectively; and   a sealer that seals the semiconductor chip, apart of the chip mounting portion, a part of the first lead, a part of the second lead, and the plurality of conductive members so that the sealer is in contact with the bonding surfaces,   wherein each of the bonding surfaces is made of a metal material,   the sealer is made of a resin material,   in a plan view, the plurality of openings are arranged so as to be adjacent to each other in the first direction,   in a plan view, each of the plurality of openings of the insulating film includes:
 a first side extending in the first direction; 
 a second side extending in the first direction and being opposite to the first side; 
 a third side extending in a second direction intersecting the first direction; and 
 a fourth side extending in the second direction and being opposite to the third side, 
   in a plan view, the fourth side of a first opening of the plurality of openings and the third side of a second opening of the plurality of openings are located so as to be adjacent to each other across a first region of the insulating film,   a first conductive member of the plurality of conductive members includes:
 a first connecting portion connected to the first electrode at the first opening of the insulating film; 
 a second connecting portion connected to the first electrode at the first opening of the insulating film; and 
 a loop portion located between the first connecting portion and the second connecting portion, the loop portion being separated from the bonding surface of the first electrode, and, 
   in the first direction, a thickness of the first region of the insulating film, the first region being sandwiched between the fourth side of the first opening and the third side of the second opening, is larger than a thickness of the loop portion of the first conductive member.   
     
     
         12 . The semiconductor device according to  claim 11 ,
 wherein, in the first direction, thicknesses of parts of the plurality of conductive members, the parts being connected to the first electrode, are different from each other.   
     
     
         13 . The semiconductor device according to  claim 11 ,
 wherein, in a plan view, an area of the first opening and an area of the second opening are different from each other.   
     
     
         14 . The semiconductor device according to  claim 11 ,
 wherein each of the plurality of conductive members has the first connecting portion, the second connecting portion, and the loop portion that are connected to the first electrode at each of the plurality of openings.   
     
     
         15 . The semiconductor device according to  claim 11 ,
 wherein, in a plan view, an outer periphery of the first region includes:
 the fourth side of the first opening; 
 the third side of the second opening; 
 a fifth side extending from an intersection between the first side and the fourth side of the first opening to an intersection between the first side and the third side of the second opening; and 
 a sixth side extending from an intersection between the second side and the fourth side of the first opening to an intersection between the second side and the third side of the second opening, and, 
   in a plan view, an area of a part of the first opening, the part not overlapping the first conductive member, is smaller than an area of the first region.   
     
     
         16 . A semiconductor device comprising:
 a semiconductor chip having an insulating film formed on a first main surface, the insulating film having a first opening exposing a first bonding surface and a second opening exposing a second bonding surface;   a first wire bonded to the first bonding surface of the semiconductor chip;   a second wire bonded to the second bonding surface of the semiconductor chip; and   a sealer that seals the semiconductor chip, the first wire, and the second wire so that the sealer is in contact with the first bonding surface and the second bonding surface of the semiconductor chip,   wherein each of the first bonding surface and the second bonding surface is made of a metal material,   the sealer is made of a resin material,   the first wire includes:
 a first connecting portion bonded to the first bonding surface; 
 a second connecting portion bonded to the first bonding surface; and 
 a first loop portion located between the first connecting portion and the second connecting portion in a first direction in a plan view, the first loop portion being separated from the first bonding surface, 
   the second wire includes:
 a third connecting portion bonded to the second bonding surface; 
 a fourth connecting portion bonded to the second bonding surface; and 
 a second loop portion located between the third connecting portion and the fourth connecting portion in a plan view, the second loop portion being separated from the second bonding surface, 
   in a plan view, the first bonding surface and the second bonding surface are arranged side by side in a second direction intersecting the first direction,   a periphery of each of the first bonding surface and the second bonding surface includes:
 a first portion closer in the second direction to one side of a wire bonded to each of the bonding surfaces; and 
 a second portion closer in the second direction to the other side of the wire, 
   in the second direction, the second portion of the first bonding surface and the first portion of the second bonding surface are located adjacent to each other across a first region of the insulating film,   in the second direction, a width of the first region is larger than a width of the first loop portion of the first wire, and   each of the width of the first region and the width of the first loop portion of the first wire is defined as a length in the second direction.   
     
     
         17 . The semiconductor device according to  claim 16 ,
 wherein, in a plan view, the first wire intersects a part of a periphery of the first opening, and the second wire intersects a part of a periphery of the second opening.   
     
     
         18 . The semiconductor device according to  claim 16 ,
 wherein, in the second direction, a maximum width of a region of the first bonding surface, the region being sandwiched between the first wire and the second portion of the first bonding surface, is smaller than a width of the first region of the insulating film.   
     
     
         19 . The semiconductor device according to  claim 16 ,
 wherein, in the second direction, the width of the first region includes a plurality of values, and   a minimum value of the plurality of values included in the width of the first region is larger than a width of the first loop portion.