Applying random nets credit in an efficient static timing analysis

Abstract

A method may include: specifying a random nets credit (RNC) statistic for nets subject to random noise in a static timing analysis of an initial integrated circuit (IC) design; calculating an upper bound for a delta delay of each net using the RNC statistic; identifying each net with a delta delay that exceeds the upper bound; identifying all nets including fan-in and fan-out cones connected to each net that exceeds the upper bound and performing a higher accuracy timing analysis for all nets that are marked. Using the upper bound for each delta delay of the nets subject to ransom noise, the delta delay of each net subject to a non-random noise, and the delta delay for all identified nets, to adjust the initial IC design, to close timing and generate a final IC design.

What is claimed is: 
     
         1 . A method, comprising:
 specifying a random net credit (RNC) statistic for a number of nets subject to a coupled random noise in a static timing analysis of an initial integrated circuit (IC) design;   performing a static timing analysis of said integrate circuit design;   calculating an upper bound for a delta delay of each of said number of nets using said RNC statistic;   identifying each of said number of nets with a delta delay that exceeds said upper bound;   identifying all nets, including fan-in cones and fan-out cones of nets, connected to each of said number of nets that exceeds said upper bound; and   performing a higher accuracy timing analysis for said all nets that are identified.   
     
     
         2 . The method of  claim 1 , said RNC statistic comprising a sum of a credit statistic based on the N largest delta delays of N nets and on how many of said N nets can switch at the same time, and of a root sum square of a credit statistic based on the M next largest delta delays of M nets and on how many of said M nets can switch at the same time, to define an RNC (N, M) statistic. 
     
     
         3 . The method of  claim 2 , said calculating of said upper bound for said delta delay of each of said number of nets comprising dividing a corresponding slack of said each of said number of nets by said RNC (N, M) statistic. 
     
     
         4 . The method of  claim 1 , said fan-in cones comprising all predecessor nets in a path from a source to each one of said number of nets with a delta delay that exceeds said upper bound, and said fan-out cones comprising all successor nets in a path from said each one of said number of nets with a delta delay that exceeds said upper bound to a sink. 
     
     
         5 . The method of  claim 1 , said performing of said higher accuracy timing analysis for said all nets that are identified including any of: refined delta delay calculations and path-based analyses based on a physical design. 
     
     
         6 . The method of  claim 1  further comprising, computing a delta delay for each net subject to a non-random noise in said IC design, and including said delta delays in said static timing analysis. 
     
     
         7 . The method of  claim 6 , further comprising using slacks from said static timing analysis and said higher accuracy timing analysis of said identified nets, to adjust said initial IC design, to close timing, and to generate a final IC design. 
     
     
         8 . A method comprising:
 specifying a random net credit (RNC) statistic for a number of nets subject to a coupled random noise in a static timing analysis of an initial integrated circuit (IC) design;   performing a static timing analysis of said integrate circuit design;   calculating a delta delay for each of said number of nets subject to said coupled random noise based on a slack of said net and said RNC statistic;   performing a timing analysis of each net subject to a non-random noise to yield a delta delay;   calculating an excess delta delay, edD, for each of said number of nets based on said calculated delta delay, said slack of each said net, and said RNC statistic;   propagating a value of one of: a sum of edDs along each path and a maximum edD along each path;   computing a maximum path delta delay value at each net based on said propagated value; and   calculating a lower bound slack for each net based on a difference between said slack of each said net and said maximum path delta delay.   
     
     
         9 . The method of  claim 8 , said RNC statistic comprising a sum of a credit statistic based on the N largest delta delays of N nets and on how many of said N nets can switch at the same time, and of a root sum square of a credit statistic based on the M next largest delta delays of M nets and on how many of said M nets can switch at the same time, to define an RNC (N, M) statistic. 
     
     
         10 . The method of  claim 9 , said delta delay for each of said number of nets being based on a slack for each said number of nets divided by said RNC (N, M) statistic. 
     
     
         11 . The method of  claim 8 , said excess delta delay, edD, for each single net(X) equaling dD(X)−slack(X)/(N+sqrt(M)), where dD(X) equals a delta delay of net(X), slack(X) equals a slack of net(X), and (N+sqrt(M)) equals said RNC (N, M) statistic. 
     
     
         12 . The method of  claim 11 , said propagating said value of one of: said sum of edDs along each path and said maximum edD along each path being defined by, respectively,
 max_edD(X)=max(max_fwd-edD(X), max_bck_edD(X)), where a combination of forward and backward propagation of the maximum edD occurs along each path, and   sum_edD(X)=sum_fwd_edD(X)+sum_bck_edD(X)−edD(X), where a combination of forward and backward propagation of the sums of edDs occurs along each path.   
     
     
         13 . The method of  claim 12 , said computing of said maximum path delta delay at each said net(X) being based on said propagated value comprising a smallest value of:
   max_path_ dD ( X )=max(slack,0)+max_ edD ( X )×( N +sqrt( M )); and
     max_path_ dD ( X )=max(slack,0)+sum_ edD ( X ).   
     
     
         14 . The method of  claim 8 , further comprising using calculations of said lower bound slack for each net to adjust said initial IC design, to close timing, and to generate a final IC design. 
     
     
         15 . A system, comprising:
 a memory that stores an integrated circuit (IC) design; and   at least one processor that performs computer readable instructions to:
 specify a random net credit (RNC) statistic for a number of nets subject to a coupled random noise in a static timing analysis of said IC design; 
 perform a static timing analysis of said IC design; 
 calculate an upper bound for a delta delay of each of said number of nets by a calculation using said RNC statistic; 
 identify each of said number of nets with a delta delay that exceeds said upper bound; 
 identify all nets, including fan-in cones and fan-out cones of nets, connected to each of said number of nets that exceeds said upper bound; and 
 perform a higher accuracy timing analysis for said all nets that are identified. 
   
     
     
         16 . The system of  claim 15 , said RNC statistic comprising a sum of credit statistic based on the N largest delta delays of N nets and on how many of said N nets can switch at the same time, and of a root sum square of credit statistic based on the M next largest delta delays of M nets and on how many of said M nets can switch at the same time, to define an RNC (N, M) statistic. 
     
     
         17 . The system of  claim 16 , calculation of said upper bound for said delta delay of each of said number of nets comprising dividing a corresponding slack of said each of said number of nets by said RNC (N, M) statistic. 
     
     
         18 . The system of  claim 15 , said fan-in cones comprising all predecessor nets in a path from a source to each one of said number of nets with a delta delay that exceeds said upper bound, and said fan-out cones comprising all successor nets in a path from said each one of said number of nets with a delta delay that exceeds said upper bound to a sink. 
     
     
         19 . The system of  claim 15 , performance of said higher accuracy timing analysis for said all nets that are identified including any of: refined delta delay calculations and path-based analyses based on a physical design. 
     
     
         20 . The system of  claim 15 , said at least one processor further performing computer readable instructions to: use calculations of said upper bound for each delta delay of each of said number of nets subject to said coupled random noise, said delta delay of each net subject to a non-random noise, and more accurate delta delay for said all nets that are identified, to adjust said IC design, to close timing, and to generate a final IC design.