Method of forming package-on-package structure

Abstract

A method of forming a package-on-package (POP) structure is provided. A laser drilling is performed on a mold compound of a first semiconductor package to form a plurality of through holes in the mold compound. A conductive layer is formed on the mold compound such that the mold compound is covered by a conductive material and the through holes are filled with the conductive material. The layer of the conductive material is grinded to expose the mold compound. A second semiconductor package is stacked on the first semiconductor package such that a plurality of metal bumps of the second semiconductor package attach to the conductive material filled in the through holes.

1 . A method of forming a package-on-package (POP) structure, the method comprising:
 performing a laser drilling on a mold compound of a first semiconductor package to form a plurality of through holes in the mold compound;   forming a conductive layer on the mold compound such that the mold compound is covered by a conductive material and the through holes are filled with the conductive material;   grinding the conductive layer to expose the mold compound; and   stacking a second semiconductor package on the first semiconductor package such that a plurality of metal bumps of the second semiconductor package attach to the conductive material filled in the through holes.   
     
     
         2 . The method of  claim 1 , wherein forming the conductive layer on the mold compound includes sputtering the conductive material on the mold compound. 
     
     
         3 . The method of  claim 1 , wherein forming the conductive layer on the mold compound includes electroplating the conductive material on the mold compound. 
     
     
         4 . The method of  claim 1 , wherein the conductive material is copper. 
     
     
         5 . The method of  claim 1 , wherein the conductive material is gold. 
     
     
         6 . The method of  claim 1 , wherein the conductive material is a copper gold alloy. 
     
     
         7 . The method of  claim 1 , wherein the first semiconductor package is a flip-chip package. 
     
     
         8 . The method of  claim 1 , wherein the first semiconductor package comprises a first die and a first substrate, a circuitry is formed in the first substrate, and the first die is electrically connected to the circuitry via a plurality of bonding wires. 
     
     
         9 . The method of  claim 1 , wherein the first semiconductor package comprises a first die, a first substrate and a plurality of conductive pads, the first die is disposed on the first substrate and encapsulated by the mold compound, and the conductive pads are exposed on bottoms of the through holes after performing the laser drilling. 
     
     
         10 . The method of  claim 9 , wherein the first semiconductor package further comprises a plurality of conductive pillars formed in the first substrate and a plurality of metal bumps formed below the first substrate, and the conductive pads are electrically connected to some of the metal bumps of the first semiconductor package via the conductive pillars. 
     
     
         11 . The method of  claim 1 , wherein the second semiconductor package comprises a second die, the first semiconductor package comprises a first die, a first substrate, a plurality of conductive pillars and a plurality of metal bumps, the first die is disposed on the first substrate and encapsulated by the mold compound, the conductive pillars are formed in the first substrate, the metal bumps of the first semiconductor package are formed below the first substrate, the conductive material filled in the through holes forms a plurality of through hole vias, and the second die is electrically connected to some of the metal bumps of the first semiconductor package via the metal bumps of the second semiconductor package, the through hole vias and the conductive pillars. 
     
     
         12 . The method of  claim 11 , wherein the second semiconductor package further comprises a plurality of pillar bumps electrically connected to the metal bumps of the second semiconductor package. 
     
     
         13 . The method of  claim 11 , wherein the second semiconductor package further comprises a second substrate, the second die is disposed on the second substrate, and the metal bumps of the second semiconductor package are formed below the second substrate. 
     
     
         14 . The method of  claim 1 , wherein the conductive material filled in the through holes forms a plurality of through hole vias, and a height of each through hole via is between 200 micrometers to 300 micrometers. 
     
     
         15 . The method of  claim 1 , wherein the conductive material filled in the through holes forms a plurality of through hole vias, and a distance between bottoms of two adjacent through hole vias is less than 300 micrometers. 
     
     
         16 . The method of  claim 1 , wherein the mold compound is epoxy molding compound. 
     
     
         17 . The method of  claim 1 , wherein the second semiconductor package is a flip-chip package. 
     
     
         18 . The method of  claim 1 , wherein the first semiconductor package is a fan-out package. 
     
     
         19 . The method of  claim 1 , wherein the second semiconductor package is a fan-out package. 
     
     
         20 . The method of  claim 1 , wherein the conductive material filled in the through holes forms a plurality of through hole vias, and the metal bumps of the second semiconductor package are bonded to the through hole vias by performing a reflow soldering process.