US2018108766A1PendingUtilityA1

Vertical power component

Assignee: ST MICROELECTRONICS TOURS SASPriority: Mar 31, 2016Filed: Dec 7, 2017Published: Apr 19, 2018
Est. expiryMar 31, 2036(~9.7 yrs left)· nominal 20-yr term from priority
Inventors:Samuel Menard
H01L 29/747H01L 29/66386H01L 29/408H10D 64/118H10D 18/021H10D 18/80
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Claims

Abstract

A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.

Claims

exact text as granted — not AI-modified
1 . A vertical power component, comprising:
 a doped silicon substrate of a first conductivity type;   a local well of a second conductivity type extending from an upper surface of the doped silicon substrate; and   on the upper surface of the doped silicon substrate, a passivation structure coating a peripheral region of the doped silicon substrate surrounding the local well, said passivation structure comprising, on top of and in contact with said peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material, the second region providing, in a surface region of the doped silicon substrate in contact with said second region, a local increase of concentration of majority carriers in the doped silicon substrate.   
     
     
         2 . The component of  claim 1 , wherein the second region is made of phosphosilicate glass (PSG). 
     
     
         3 . The component of  claim 1 , wherein the first region is made of silicon oxide. 
     
     
         4 . The component of  claim 1 , wherein the first region is made of lead-filled glass. 
     
     
         5 . The component of  claim 1 , wherein one of the first and second regions of the passivation structure is a layer coating said peripheral region of the doped silicon substrate, interrupted by a ring-shaped opening arranged opposite a central portion of said peripheral region of the doped silicon substrate, the other region of the passivation structure being a ring-shaped strip arranged in said opening. 
     
     
         6 . A method of manufacturing a vertical power component inside and on top of a doped silicon substrate of a first conductivity type, comprising the steps of:
 forming a local well of a second conductivity type extending from an upper surface of the doped silicon substrate; and   forming, on the upper surface side of the doped silicon substrate, a passivation structure coating a peripheral region of the doped silicon substrate surrounding the local well, said passivation structure comprising, on top of and in contact with said peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material, the second region providing, in a surface region of the doped silicon substrate in contact with said second region, a local increase of the concentration of majority carriers in the doped silicon substrate.   
     
     
         7 . The method of  claim 6 , wherein the second region is made of phosphosilicate glass, the forming of the second region comprising a step of depositing phosphosilicate glass at the surface of said peripheral region of the doped silicon substrate, followed by a step of annealing at a temperature higher than 500° C.

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