Solid-state imaging device and electronic apparatus

Abstract

A solid-state imaging device and method of making a solid-state imaging device are described herein. By way of example, the solid-state imaging device includes a first wiring layer formed on a sensor substrate and a second wiring layer formed on a circuit substrate. The sensor substrate is coupled to the circuit substrate, the first wiring layer and the second wiring layer being positioned between the sensor substrate and the circuit substrate. A first electrode is formed on a surface of the first wiring layer, and a second electrode is formed on a surface of the second wiring layer. The first electrode is in electrical contact with the second electrode.

1 . A solid-state imaging device comprising:
 a first wiring layer formed on a sensor substrate; and   a second wiring layer formed on a circuit substrate, wherein   the sensor substrate is coupled to the circuit substrate, the first wiring layer and the second wiring layer being positioned between the sensor substrate and the circuit substrate,   a first electrode is formed on a surface of the first wiring layer,   a second electrode is formed on a surface of the second wiring layer, and   the first electrode is in electrical contact with the second electrode.   
     
     
         2 . The solid-state imaging device according to  claim 1 , wherein
 a floating diffusion region is formed in the sensor substrate, and a first electrical conductor connects the floating diffusion region to the first electrode.   
     
     
         3 . The solid-state imaging device according to  claim 1 , wherein
 a second electrical conductor connects the second electrode to a gate electrode of an amplification transistor.   
     
     
         4 . The solid-state imaging device according to  claim 1 , wherein
 a first photodiode and a second photodiode are formed in the sensor substrate, the first photodiode and the second photodiode sharing an amplification transistor.   
     
     
         5 . The solid-state imaging device according to  claim 1 , wherein
 a width of a region in which the first electrode and the second electrode are formed smaller in a direction parallel to a surface of the first wiring layer than a width of a region in which the first photodiode and the second photodiode are formed.   
     
     
         6 . The solid-state imaging device according to  claim 2 , wherein
 a cross-sectional area of the first electrode is greater than a cross-sectional area of the first electrical conductor in a plane parallel to a surface of the first wiring layer.   
     
     
         7 . The solid-state imaging device according to  claim 3 , wherein
 a cross-sectional area of the second electrode is greater than a cross-sectional area of the second electrical conductor in a plane parallel to a surface of the first wiring layer.   
     
     
         8 . The solid-state imaging device according to  claim 2 , wherein
 a cross-sectional area of at least one of the first electrode or the second electrode is greater in a plane parallel to a surface of the first wiring layer than a cross-sectional area of the floating diffusion region.   
     
     
         9 . The solid-state imaging device according to  claim 1 , wherein
 the first electrode includes a first conductor layer extending in a first direction parallel to a surface of the first wiring layer, and   the second electrode includes a second conductor layer extending in a second direction parallel to a surface of the second wiring layer.   
     
     
         10 . The solid-state imaging device according to  claim 9 , wherein
 the first electrode is rectangular in shape,   the second electrode is rectangular in shape,   and the first direction is perpendicular to the second direction.   
     
     
         11 . The solid-state imaging device according to  claim 1 , wherein
 the first electrode includes a first conductor layer portion formed in a first direction parallel to a surface of the first wiring layer and a second conductor layer portion formed in a second direction parallel to the surface of the first wiring layer, the first conductor layer portion intersecting the second conductor layer portion and the first direction parallel to the surface of the first wiring layer being perpendicular to the second direction parallel to the surface of the first wiring layer,   the second electrode includes a third conductor layer portion formed in a first direction parallel to a surface of the second wiring layer and a fourth conductor layer portion formed in a second direction parallel to the surface of the second wiring layer, the third conductor layer portion intersecting the fourth conductor layer portion and the first direction parallel to the surface of the second wiring layer being perpendicular to the second direction parallel to the surface of the second wiring layer, and   the first conductor layer portion is parallel to the third conductor layer portion and the second conductor layer portion is parallel to the fourth conductor layer portion.   
     
     
         12 . The solid-state imaging device according to  claim 1 , wherein
 the first electrode is formed in a first lattice shape,   the second electrode is formed in a second lattice shape, and   a center of the first electrode is offset from a center of the second electrode in a direction parallel to a surface of the first wiring layer.   
     
     
         13 . The solid-state imaging device according to  claim 1 , wherein
 the first electrode is formed in a first mesh shape,   the second electrode is formed in a second mesh shape, and   a center of the first electrode is offset from a center of the second electrode in a direction parallel to a surface of the first wiring layer.   
     
     
         14 . A solid-state imaging device comprising:
 a sensor substrate is bonded to a circuit substrate, a first wiring layer being formed on a surface of the sensor substrate and a second wiring layer being formed on a surface of the circuit substrate, the first wiring layer and the second wiring layer being between the sensor substrate and the circuit substrate, wherein   a first contact electrode is formed on a surface of the first wiring layer opposite from the sensor substrate and a second electrode is formed on a surface of the second wiring layer opposite from the circuit substrate, and   the first electrode is in electrical contact with the second electrode.   
     
     
         15 . The solid-state imaging device according to  claim 14 , wherein
 the first electrode includes a first conductor layer extending in a first direction parallel to a surface of the first wiring layer,   the second electrode includes a second conductor layer extending in a second direction parallel to a surface of the second wiring layer.   
     
     
         16 . The solid-state imaging device according to  claim 15 , wherein
 the first electrode is rectangular in shape,   the second electrode is rectangular in shape,   and the first direction is perpendicular to the second direction.   
     
     
         17 . The solid-state imaging device according to  claim 14 , wherein
 the first electrode includes a first conductor layer portion formed in a first direction parallel to a surface of the first wiring layer and a second conductor layer portion formed in a second direction parallel to the surface of the first wiring layer, the first conductor layer portion intersecting the second conductor layer portion and the first direction parallel to the surface of the first wiring layer being perpendicular to the second direction parallel to the surface of the first wiring layer,   the second electrode includes a third conductor layer portion formed in a first direction parallel to a surface of the second wiring layer and a fourth conductor layer portion formed in a second direction parallel to the surface of the second wiring layer, the third conductor layer portion intersecting the fourth conductor layer portion and the first direction parallel to the surface of the second wiring layer being perpendicular to the second direction parallel to the surface of the second wiring layer, and   the first conductor layer portion is parallel to the third conductor layer portion and the second conductor layer portion is parallel to the fourth conductor layer portion.   
     
     
         18 . The solid-state imaging device according to  claim 14 , wherein
 the first electrode is formed in a first lattice shape,   the second electrode is formed in a second lattice shape, and   a center of the first electrode is offset from a center of the second electrode in a direction parallel to a surface of the first wiring layer.   
     
     
         19 . The solid-state imaging device according to  claim 14 , wherein
 the first electrode is formed in a first mesh shape,   the second electrode is formed in a second mesh shape, and   a center of the first electrode is offset from a center of the second electrode in a direction parallel to a surface of the first wiring layer.   
     
     
         20 . A method for making a solid-state imaging device, the method comprising the steps of:
 forming a first wiring layer on a sensor substrate;   forming a second wiring layer on a circuit substrate;   forming a first electrode on a surface of the first wiring layer;   forming a second electrode on a surface of the second wiring layer; and   coupling the sensor substrate to the circuit substrate with the first wiring layer and the second wiring layer being between the sensor substrate and the circuit substrate.   
     
     
         21 . The method according to  claim 20 , wherein
 a floating diffusion region is formed in the sensor substrate, and a first electrical conductor is formed to connect the floating diffusion region to the first electrode.   
     
     
         22 . The method according to  claim 20 , wherein
 a second electrical conductor is formed to connect the second electrode to a gate electrode of an amplification transistor.   
     
     
         23 . The method according to  claim 20 , wherein
 a first photodiode and a second photodiode are formed in the sensor substrate, the first photodiode and the second photodiode sharing an amplification transistor.   
     
     
         24 . The method according to  claim 20 , wherein
 a width of region in which the first electrode and the second electrode are formed to be smaller in a direction parallel to a surface of the first wiring layer than a width of a region in which the first photodiode and the second photodiode are formed.   
     
     
         25 . The method according to  claim 21 , wherein
 a cross-sectional area of the first electrode is formed to be greater than a cross-sectional area of the first electrical conductor in a plane parallel to a surface of the first wiring layer.   
     
     
         26 . The method according to  claim 22 , wherein
 a cross-sectional area of the second electrode is formed to be greater than a cross-sectional area of the second electrical conductor in a plane parallel to a surface of the first wiring layer.   
     
     
         27 . The method according to  claim 21 , wherein
 a cross-sectional area of at least one of the first electrode or the second electrode is formed to be greater in a plane parallel to a surface of the first wiring layer than a cross-sectional area of the floating diffusion region.   
     
     
         28 . The method according to  claim 20 , wherein
 the first electrode is formed to include a first conductor layer extending in a first direction parallel to a surface of the first wiring layer, and   the second electrode is formed to include a second conductor layer extending in a second direction parallel to a surface of the second wiring layer.   
     
     
         29 . The method according to  claim 28 , wherein
 the first electrode is formed to be rectangular in shape,   the second electrode is formed to be rectangular in shape,   and the first direction is perpendicular to the second direction.   
     
     
         30 . The method according to  claim 20 , wherein
 the first electrode is formed to include a first conductor layer portion formed in a first direction parallel to a surface of the first wiring layer and a second conductor layer portion formed in a second direction parallel to the surface of the first wiring layer, the first conductor layer portion intersecting the second conductor layer portion and the first direction parallel to the surface of the first wiring layer being perpendicular to the second direction parallel to the surface of the first wiring layer,   the second electrode is formed to include a third conductor layer portion formed in a first direction parallel to a surface of the second wiring layer and a fourth conductor layer portion formed in a second direction parallel to the surface of the second wiring layer, the third conductor layer portion intersecting the fourth conductor layer portion and the first direction parallel to the surface of the second wiring layer being perpendicular to the second direction parallel to the surface of the second wiring layer, and   the first conductor layer portion is formed to be parallel to the third conductor layer portion and the second conductor layer portion is formed to be parallel to the fourth conductor layer portion.   
     
     
         31 . The method according to  claim 20 , wherein
 the first electrode is formed in a first lattice shape,   the second electrode is formed in a second lattice shape, and   a center of the first electrode is formed to be offset from a center of the second electrode in a direction parallel to a surface of the first wiring layer.   
     
     
         32 . The method according to  claim 20 , wherein
 the first electrode is formed in a first mesh shape,   the second electrode is formed in a second mesh shape, and   a center of the first electrode is formed to be offset from a center of the second electrode in a direction parallel to a surface of the first wiring layer.