Flash memory device and manufacture thereof

Abstract

A flash memory device and its manufacturing method, which is related to semiconductor techniques. The flash memory device comprises: a substrate; and a memory unit on the substrate, comprising: a channel structure on the substrate, wherein the channel structure comprise, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure, wherein there exist cavities between neighboring gate structures; a support structure supporting the gate structures; and a plurality of gate contact components each contacting a gate structure. The cavities between neighboring gate structures lower the parasitic capacitance, reduce inter-gate interference, and suppress the influence from writing or erasing operations of nearby memory units.

What is claimed is: 
     
         1 . A flash memory device, comprising:
 a substrate; and   a memory unit on the substrate, comprising:
 a channel structure on the substrate, wherein the channel structure comprises, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; 
 a plurality of gate structures wrapped around the channel structure and arranged along an axis of symmetry of the channel structure, with cavities between neighboring gate structures; 
 a support structure supporting the gate structures; and 
 a plurality of gate contact components each contacting a gate structure. 
   
     
     
         2 . The device of  claim 1 , wherein the support structure comprises at least one pillar support component comprising a pillar kernel and a cover layer around the pillar kernel. 
     
     
         3 . The device of  claim 2 , wherein the pillar kernel is made of silicon dioxide and the cover layer is made of undoped polycrystalline silicon. 
     
     
         4 . The device of  claim 1 , wherein the channel structure further comprises an anti-etching layer wrapped around the side surfaces of the charge capture layer. 
     
     
         5 . The device of  claim 4 , wherein the anti-etching layer is made of a High Temperature Oxide (HTO), wherein the HTO is a silicon oxide formed in a temperature range from 300 to 500 Celsius degree. 
     
     
         6 . The device of  claim 1 , wherein the channel structure further comprises a channel kernel surrounded by the channel layer. 
     
     
         7 . The device of  claim 1 , wherein the memory unit comprises a plurality of channel structures arranged in the gate structures. 
     
     
         8 . The device of  claim 2 , wherein each of the gate structures comprises a gate, a work function regulation layer on the surface of the gate, and a high-K dielectric layer on the surface of the work function regulation layer, wherein a first portion of the high-K dielectric layer is located between the gate and the channel structure and a second portion of the high-K dielectric layer is located between the gate and the pillar support component. 
     
     
         9 . The device of  claim 8 , wherein the gate structures form a staircase pattern, and wherein each of the gate contact components contacts the gate of a corresponding gate structure at a step of the staircase pattern, and each of the pillar support components is also located on a step of the staircase pattern and separating from the gate contact components. 
     
     
         10 . The device of  claim 1 , further comprising:
 a plurality of the memory units separated from each other;   a groove metal filling layer; and   an interval layer, wherein both the groove metal filling layer and the interval layer are located on the substrate between the neighboring memory units, and the interval layer separates the groove metal filling layer from the gate structures.   
     
     
         11 . The device of  claim 10 , wherein the substrate further comprises a doped region in the substrate contacting the groove metal filling layer. 
     
     
         12 . The device of  claim 1 , further comprises an inter-layer dielectric layer on the gate structures wrapped around the support structure and the gate contact components. 
     
     
         13 . A method for manufacturing a flash memory device, comprising:
 providing a substrate;   forming a plurality of first sacrificial layers and a plurality of second sacrificial layers stacked in an alternating manner, wherein the first sacrificial layers contain material that is different from the second sacrificial layers;   forming a support structure in the first sacrificial layers and the second sacrificial layers;   forming a first through-hole exposing an upper surface of the substrate by etching the first sacrificial layers and the second sacrificial layers;   forming a channel structure in the first through-hole, wherein the channel structure comprises, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer;   forming a plurality of first cavities by removing the first sacrificial layers;   forming a plurality of gate structures in the first cavities;   forming a plurality of second cavities between neighboring gate structures by removing the second sacrificial layers; and   forming a plurality of gate contact components each connecting to a gate structure.   
     
     
         14 . The method of  claim 13 , wherein the support structure comprises at least one pillar support component, wherein the pillar support component comprises a pillar kernel and a common cover layer wrapped around the pillar kernel. 
     
     
         15 . The method of  claim 14 , wherein the first sacrificial layers and the second sacrificial layers form a staircase pattern, and wherein forming a support structure in the first sacrificial layers and the second sacrificial layers comprises:
 forming a first dielectric layer on the staircase pattern comprising the first sacrificial layers and the second sacrificial layers;   forming an opening exposing the upper surface of the substrate by etching the first dielectric layer, the first sacrificial layers and the second sacrificial layers;   forming the pillar support component in the opening; and   forming a second dielectric layer covering the pillar support component on the first dielectric layer.   
     
     
         16 . The method of  claim 15 , wherein forming the pillar support component in the opening comprises:
 forming a first cover layer on a side surface and the bottom of the opening;   forming the pillar kernel filling the opening on the first cover layer;   forming a pillar cavity by etching back a portion of the pillar kernel; and   forming a second cover layer filling the pillar cavity, wherein the first cover layer and the second cover layer form the common cover layer wrapped around the pillar kernel.   
     
     
         17 . The method of  claim 14 , wherein the pillar kernel is made of silicon dioxide and the common cover layer is made of undoped polycrystalline silicon. 
     
     
         18 . The method of  claim 13 , wherein the first sacrificial layers are made of silicon nitride and the second sacrificial layers are made of silicon dioxide. 
     
     
         19 . The method of  claim 13 , wherein the channel structure further comprises an anti-etching layer wrapped around the charge capture layer. 
     
     
         20 . The method of  claim 19 , wherein the anti-etching layer is made of a High Temperature Oxide (HTO), wherein the HTO is a silicon oxide formed in a temperature range from 300 to 500 Celsius degree.