Method and device for storing an image into a memory

Abstract

Aspects of the disclosure provide a method and device for storing an input image into a memory. The disclosure describes allocating one or more frame buffers in the memory. The disclosure further describes dividing the input image into access units corresponding to subsets of the input image and allocating a main portion and a secondary portion in the frame buffer for each of the access units, wherein at least one of the secondary portions is not sequentially located after its respective main portion within the frame buffer. The disclosure also describes compressing the access units into compressed access units and storing each of the compressed access units into its respective main portion, and if a size of the compressed access unit exceeds a size of the main portion, then storing a remainder of the compressed access unit into its respective secondary portion.

What claimed is: 
     
         1 . A method for storing an input image into a memory, comprising:
 allocating one or more frame buffers in the memory;   dividing the input image into access units corresponding to subsets of the input image and allocating a main portion and, a secondary portion in the frame buffer for each of the access units, wherein at least one of the secondary portions is not sequentially located after its respective main portion within the frame buffer;   compressing the access units into compressed access units; and   storing each of the compressed access units into its respective main portion, and if a size of the compressed access unit exceeds a size of the main portion, then storing a remainder of the compressed access unit into its respective secondary portion.   
     
     
         2 . The method of  claim 1 , wherein the memory has a sequence of memory blocks separated by memory boundaries at addresses that are multiples of a memory block size and the memory block size is determined based on characteristics of the memory and devices accessing the memory. 
     
     
         3 . The method of  claim 2 , wherein a size of the main portions is one or multiples of the memory block size and starting addresses of the main portions are aligned to memory boundaries. 
     
     
         4 . The method of  claim 2 , wherein a size of the main portions is a fraction of the memory block size and each main portion is located within a respective memory block. 
     
     
         5 . The method of  claim 2 , wherein a size of the secondary portions is a fraction of the memory block size and secondary portions are grouped into one or more secondary portion groups. 
     
     
         6 . The method of  claim 5 , wherein the one or more secondary portion groups have a size being one or multiples of the memory block size and the first secondary portion of each secondary portion group has a starting address aligned to a memory boundary. 
     
     
         7 . The method of  claim 2 , wherein a plurality of main portions and secondary portions are arranged in a predetermined pattern to form a superblock having a size that is one or multiples of the memory block size and the main and secondary portions in the frame buffer are arranged by sequentially positioning a plurality of superblocks adjacent to each other. 
     
     
         8 . The method of  claim 2 , wherein the memory block size is selected to be 32, 64, 128, 256, 512, 1K, 2K, or 4K bytes. 
     
     
         9 . The method of  claim 1 , wherein the input image is a still image or a video frame. 
     
     
         10 . A device for storing an input image, comprising:
 a memory configured to store one or more frame buffers;   a memory distribution device configured to receive the input image, allocate a frame buffer in the memory to store the input image, divide the input image into access units corresponding to subsets of the input image, and allocate a main portion and a secondary portion in the frame buffer for each of the access units, wherein at least one of the secondary portions is not sequentially located after its respective main portion within the frame buffer; and   a memory controller configured to store, in response to instructions of the memory distribution device, each of the compressed access units into its respective main portion, and if a size of the, compressed access unit exceeds a size of the main portion, then store a remainder of the compressed access unit into its respective secondary portion.   
     
     
         11 . The device of  claim 10 , wherein the memory has a sequence of memory blocks separated by memory boundaries at addresses that are multiples of a memory block size and the memory block size is determined based on characteristics of the memory and devices accessing the memory including the memory distribution device. 
     
     
         12 . The device of  claim 11 , wherein the memory distribution device is configured to select a size of the main portions to be one or multiples of the memory block size and align starting addresses of the main portions to memory boundaries. 
     
     
         13 . The device of  claim 11 , wherein the memory distribution device is configured to select a size of the main portions to be a fraction of the memory block size and position each main portion within a respective memory block. 
     
     
         14 . The device of  claim 11 , wherein the memory distribution device is configured to a select a size of the secondary portions to be a fraction of the memory block size and group secondary portions into one or more secondary portion groups. 
     
     
         15 . The device of  claim 14 , wherein the memory distribution devices configured to select a size of the one or more secondary portion groups to be one or multiples of the memory block size and align the starting address of the first secondary portion of each secondary portion group to a memory boundary. 
     
     
         16 . The device of  claim 11 , wherein the memory distribution device is configured to arrange a plurality of main portions and secondary portions in a predetermined pattern to form a superblock having a size being one or multiples, of the memory block size and further position a plurality of superblocks adjacent to each other in the frame buffer. 
     
     
         17 . The device of  claim 10 , wherein the memory is located on a different integrated chip than the memory distribution device. 
     
     
         18 . The device of  claim 10 , wherein the memory distribution device is integrated into a video codec. 
     
     
         19 . The device of claim wherein the memory, distribution device is configured to determine the memory block size to be 32, 64, 128, 256, 512, 1K, 2K, or 4K bytes. 
     
     
         20 . A non-transitory computer readable medium having computer readable instructions stored thereon which, when executed by a processing circuit, cause the processing circuit to perform a method, the method comprising:
 allocating one or more frame buffers in the memory;   dividing the input image into access units corresponding to subsets of the input image and allocating a main portion and a secondary portion in the frame buffer for each of the access units, wherein at least one of the secondary portions is not sequentially located after its respective main portion within the frame buffer;   compressing the access units into compressed access units; and,   storing each of the compressed access units into its respective main portion, and if a size of the compressed access unit exceeds a size of the main portion, then storing a remainder of the compressed access unit into its respective secondary portion.