Metalization repair in semiconductor wafers

Abstract

Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor wafer, wherein the feature includes a first conductive material and a surface having a planar region and non-planar regions. The method further includes forming a metal conductive liner over the non-planar regions. The method further includes applying a second conductive material metal layer over said the conductive liner. The method further includes recessing the second conductive material to be substantially planar with the planar region.

1 . A method for repairing features of a host semiconductor wafer, the method comprising:
 forming a feature of the host semiconductor wafer, wherein forming the feature comprises one or more operations configured to planarize an exposed surface of the feature, wherein implementing the one or more operations results in the feature comprising a first conductive material and the exposed surface, wherein the exposed surface formed by the one or more operations comprises a planar region and unintended defects comprising unintended non-planar regions;   forming a conductive liner over at least the non-planar regions;   applying a second conductive material over at least the conductive liner; and   recessing the second conductive material to be substantially planar with the planar region.   
     
     
         2 . The method of  claim 1 , wherein the first conductive material comprises copper. 
     
     
         3 . The method of  claim 1 , wherein the conductive liner comprises tantalum, cobalt, ruthenium, or nitrides thereof. 
     
     
         4 . The method of  claim 1 , wherein recessing the second conductive material comprises applying a chemical mechanical planarization (CMP) to the second conductive material. 
     
     
         5 . The method of  claim 1 , wherein the conductive liner comprises a thickness dimension within a range from about 10 nanometers to about 300 nanometers. 
     
     
         6 . The method of  claim 1 , wherein the second conductive material comprises copper. 
     
     
         7 . The method of  claim 1  further comprising annealing the second conductive material. 
     
     
         8 . The method of  claim 7 , wherein annealing the second conductive material comprises reflowing the second conductive material. 
     
     
         9 . The method according to  claim 8 , wherein the annealing is performed at a temperature within a range from approximately 200 Celsius degrees to approximately 300 Celsius degrees. 
     
     
         10 . A method for repairing features of a host semiconductor wafer, the method comprising:
 forming a feature of the host semiconductor wafer, wherein the feature comprises a first conductive material and a surface having a planar region and non-planar regions;   determining a defect level of the feature, wherein the defect level corresponds to a characteristic of the non-planar regions;   comparing the defect level to a threshold;   applying a first repair methodology to the feature if the defect level is below the threshold; and   applying a second repair methodology to the feature if the defect level is above the threshold.   
     
     
         11 . The method of  claim 10 , wherein the second repair methodology comprises:
 forming a conductive liner over at least the non-planar regions;   applying a second conductive material over at least the conductive liner; and   recessing the second conductive material to be substantially planar with the planar region.   
     
     
         12 . The method of  claim 11 , wherein the first conductive material comprises copper. 
     
     
         13 . The method of  claim 11 , wherein the conductive liner comprises tantalum, cobalt, ruthenium, or nitrides thereof. 
     
     
         14 . The method of  claim 11 , wherein recessing the second conductive material comprises applying a chemical mechanical planarization (CMP) to the second conductive material. 
     
     
         15 . The method of  claim 11 , wherein the conductive liner comprises a thickness dimension within a range of about 10 nm to about 300 nm. 
     
     
         16 . The method of  claim 11 , wherein the second conductive material comprises copper. 
     
     
         17 . The method of  claim 11 , wherein the second repair methodology further comprises annealing the first conductive material, the second conductive material and the conductive liner. 
     
     
         18 . The method of  claim 17 , wherein the annealing is performed at a temperature comprising approximately 100 Celsius degrees. 
     
     
         19 . The method of  claim 10 , wherein the second repair methodology comprises applying a current to first conductive material to induce a plating of the first conductive material. 
     
     
         20 . A feature of a host semiconductor wafer, the feature comprising:
 a first conductive material;   a top surface of the first conductive material, wherein the top surface comprises a planar region and unintended defects comprising unintended non-planar regions;   a conductive liner over the non-planar regions; and   a second conductive material over the conductive liner.