Phase-change memory cell

Abstract

Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.

1 . An assembly of two phase-change memory cells, comprising:
 a first conductive via and a second conductive via each made of a first metal;   a central conductive via located between the first and second conductive vias, a lower portion of the central conductive via being made of the first metal and an upper portion of the central conductive via being made of a second metal;   a first resistive element on the first conductive via and a second resistive element on the second conductive via; and   a layer of phase-change material in contact with a top portion of each of the first and second resistive elements.   
     
     
         2 . The assembly of two phase-change memory cells of  claim 1 , wherein the first metal is tungsten and the second metal is copper. 
     
     
         3 . The assembly of two phase-change memory cells of  claim 1 , wherein the central via has a shape in the form of an elongated conductive strip. 
     
     
         4 . The assembly of two phase-change memory cells of  claim 1 , wherein the first and second conductive vias are each formed of a lower portion made of the first metal and of an upper portion made of the second metal. 
     
     
         5 . The assembly of two phase-change memory cells of  claim 1 , comprising a first transistor and a second transistor, a drain of the first transistor being in contact with the first conductive via, a source of the first transistor being in contact with the central conductive via, a source of the second transistor being in contact with the central conductive via, and a drain of the second transistor being in contact with the second conductive via. 
     
     
         6 . The assembly of two phase-change memory cells of  claim 5 , wherein the sources of the first and second transistors are a shared source. 
     
     
         7 . The assembly of two phase-change memory cells of  claim 1 , wherein each of the first and second resistive elements has an L-shape including a first leg in contact with a respective one of the first and second conductive vias and a second leg, extending perpendicular to the first leg, in contact with the layer of phase-change material. 
     
     
         8 . The assembly of two phase-change memory cells of  claim 1 , wherein the phase-change material is an alloy comprising germanium, antimony, and tellurium. 
     
     
         9 . A phase-change memory, comprising a plurality of cells, wherein phase-change memory cells of the plurality of cells are formed on either side of a common central conductive via and wherein an assembly of two phase-change memory cells comprises:
 a first conductive via and a second conductive via each made of a first metal;   the central conductive via located between the first and second conductive vias, a lower portion of the central conductive via being made of the first metal and an upper portion of the central conductive via being made of a second metal;   a first resistive element on the first conductive via and a second resistive element on the second conductive via; and   a layer of phase-change material in contact with a top portion of each of the first and second resistive elements.   
     
     
         10 . The memory of  claim 9 , comprising:
 a first electrode formed on the phase-change material opposite the first and second conductive vias; and   a second electrode in contact with the central conductive via.   
     
     
         11 . The memory of  claim 9 , wherein the phase-change material is an alloy comprising germanium, antimony, and tellurium. 
     
     
         12 . The memory of  claim 9 , wherein the first metal is tungsten and the second metal is copper. 
     
     
         13 . The memory of  claim 9 , wherein the central via has a shape in the form of an elongated conductive strip. 
     
     
         14 . The memory of  claim 9 , wherein the first and second conductive vias are each formed of a lower portion made of the first metal and of an upper portion made of the second metal. 
     
     
         15 . The memory of  claim 9 , comprising a first transistor and a second transistor, a drain of the first transistor being in contact with the first conductive via, a source of the first transistor being in contact with the central conductive via, a source of the second transistor being in contact with the central conductive via, and a drain of the second transistor being in contact with the second conductive via. 
     
     
         16 . The memory of  claim 15 , wherein the sources of the first and second transistors are a shared source. 
     
     
         17 . The memory of  claim 9 , wherein each of the first and second resistive elements has an L-shape including a first leg in contact with a respective one of the first and second conductive vias and a second leg, extending perpendicular to the first leg, in contact with the layer of phase-change material. 
     
     
         18 - 21 . (canceled) 
     
     
         22 . A circuit, comprising:
 a first phase-change memory cell, comprising:
 a first conductive via made of tungsten; 
 a first resistive element in contact with a first end of the first conductive via; 
 a first transistor having a source-drain path connected between a second end of the first conductive via and a source contact; and 
 a first layer of phase-change material in contact with the first resistive element; 
   a second phase-change memory cell, comprising:
 a second conductive via made of tungsten; 
 a second resistive element in contact with a first end of the second conductive via; 
 a second transistor having a source-drain path connected between a second end of the second conductive via and the source contact; and 
 a second layer of phase-change material in contact with the second resistive element; and 
   wherein said source contact comprises a central conductive via having a lower portion made of tungsten and an upper portion made of copper.   
     
     
         23 . The circuit of  claim 22 , wherein the first and second conductive vias are each formed of a lower portion made of tungsten and of an upper portion made of copper. 
     
     
         24 . The circuit of  claim 22 , wherein each of the first and second resistive elements has an L-shape including a first leg in contact with a respective one of the first and second conductive vias and a second leg, extending perpendicular to the first leg, in contact with a respective one of the first and second layers of phase-change material. 
     
     
         25 . The circuit of  claim 22 , wherein the phase-change material is an alloy comprising germanium, antimony, and tellurium. 
     
     
         26 . The circuit of  claim 22 , wherein the first and second layers of phase-change material are a same layer.