Semiconductor device

Abstract

A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate;   an electrode layer disposed on the substrate; and   a tri-layered gate-control stack sandwiched between the substrate and the electrode layer, the tri-layered gate-control stack comprising:
 an anti-ferroelectric (AFE) layer disposed on the substrate; 
 a mid-gap metal layer sandwiched between the AFE layer and the substrate; and 
 a ferroelectric layer sandwiched between the AFE layer and the mid-gap metal layer. 
   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the electrode layer comprises at least a work function metal layer. 
     
     
         3 . The semiconductor device according to  claim 1  further comprising an oxide liner layer sandwiched between the mid-gap metal layer of the tri-layered gate-control stack and the substrate. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the ferroelectric layer comprises a material selected from the group consisting of lead zirconate titanate (bZrTiO 3 , PZT), lead lanthanum zirconate titanate (PbLa(TiZr)O 3 , PLZT), strontium bismuth tantalite (SrBiTa 2 O 9 , SBT), bismuth lanthanum titanate ((BiLa) 4 Ti 3 O 12 ,BLT), and barium strontium titanate (BaSrTiO3, BST). 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the mid-gap metal layer comprises metal nitride. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the AFE layer comprises a material selected from the group consisting of lead indium niobate (Pb(InNb)O 3 ), niobium-sodium oxide (NbNaO 3 ), lead zirconate (ZrPbO 3 ), lead lanthanum zirconate titanate (TiZrLaPbO 3 ), lead zirconate titanate (TiZrPbO 3 ), ammonium dihydrogen phosphate (NH 4 H 2 PO 4 , ADP), and ammonium dihydrogen arsenate (NH 4 H 2 AsO 4 , ADA). 
     
     
         7 . The semiconductor device according to  claim 1 , further comprising a bottom barrier layer and an etch stop layer sandwiched between the tri-layered gate-control stack and the electrode layer. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein the tri-layered gate-control stack comprises a U shape.