US2018081814A1PendingUtilityA1

Quality of cache management in a computer

Assignee: IBMPriority: Sep 22, 2016Filed: Feb 23, 2017Published: Mar 22, 2018
Est. expirySep 22, 2036(~10.2 yrs left)· nominal 20-yr term from priority
G06F 12/0811G06F 2212/602G06F 12/0862G06F 9/3802G06F 9/30047G06F 2212/283
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Claims

Abstract

Embodiments here relate to managing a cache by exploiting a cache line hierarchy is provided. Managing the cache includes reading cache references of a first task from a cache reference save area of a first task data structure in response to a context switch. Further, managing the cache includes prefetching and restoring cache lines of the first task to the cache based on the cache references. Note that the cache lines can be predetermined from a plurality of cache lines associated with the first task during an extraction operation with respect to the first task and the cache line hierarchy.

Claims

exact text as granted — not AI-modified
1 . A method of managing a cache by exploiting a cache line hierarchy, the method comprising:
 reading, by a processor, cache references of a first task from a cache reference save area of a first task data structure in response to a context switch;   prefetching and restoring, by the processor, cache lines of the first task to the cache based on the cache references,   wherein the cache lines were predetermined from a plurality of cache lines associated with the first task during an extraction operation with respect to the first task and the cache line hierarchy.   
     
     
         2 . The method of  claim 1 , comprising:
 extracting, by a processor coupled to a memory, cache references of a second task.   
     
     
         3 . The method of  claim 2 , wherein the extracting by the processor includes executing an extract instruction definition comprising a code defining the extract instruction definition for prefetching, a first field specifying a register with an identification of data items related to the second task, a base field designating a base register, and a displacement field designating a displacement. 
     
     
         4 . The method of  claim 1 , wherein the prefetching is performed after the context switch and before an execution of first task. 
     
     
         5 . The method of  claim 1 , wherein the prefetching by the processor includes executing a prefetch instruction definition comprising a code defining the prefetch instruction definition for prefetching, a first field specifying a register with an identification of data items related to the first task, a base field designating a base register, and a displacement field designating a displacement. 
     
     
         6 . The method of  claim 5 , wherein the base register and the base register form an address of a memory location within a register save area of the data structure of the first task. 
     
     
         7 . The method of  claim 1 , wherein the context switch comprises changing from an execution of a second task to an execution of the first task. 
     
     
         8 . The method of  claim 1 , wherein the exploiting of the cache line hierarchy comprises prefetching and restoring hot cache lines as the cache lines of the first task.

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