US2018081697A1PendingUtilityA1

System for re-enumeration of usb 3.0 compatible peripheral devices

Assignee: CYPRESS SEMICONDUCTOR CORPPriority: Sep 29, 2011Filed: Aug 24, 2017Published: Mar 22, 2018
Est. expirySep 29, 2031(~5.2 yrs left)· nominal 20-yr term from priority
G06F 11/3055G06F 11/3041G06F 13/426G06F 2213/0042G06F 9/4413G06F 13/4295G06F 9/4411G06F 13/385
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Claims

Abstract

Described herein is a system comprising a peripheral device that is connected to a host device over a bus compatible with USB 3.0. The host device comprises a reduced functionality USB host controller configured to perform a set of one or more preprogrammed functions from the USB 3.0 specification, and a universal asynchronous receiver and transmitter (UART) configured to sample USB response data received from the peripheral device over the bus.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 - 5 . (canceled) 
     
     
         6 . A communication system comprising:
 a peripheral device comprising a first communication interface circuit; and   a host device comprising:
 a second communication interface circuit, 
 a processor circuit coupled to the first communication interface circuit, and 
 a sampling circuit coupled to the second communication interface circuit and the processor circuit, 
 wherein the second communication interface circuit provides a state signal to the processor circuit in response to a connection of the first and second communication interface circuits. 
   
     
     
         7 . The communication system of  claim 6 , wherein the first and second communication interface circuits are configured to communicate according to Universal Serial Bus (USB) protocols. 
     
     
         8 . The communication system of  claim 6 , wherein the host device further comprises a non-transitory storage medium coupled to the processor circuit, the non-transitory storage medium comprising a plurality of memory locations corresponding to data received from the sampling circuit. 
     
     
         9 . The communication system of  claim 6 , further comprising a serializer/deserializer coupled between the processing circuit and the second communication interface circuit. 
     
     
         10 . The communication system of  claim 6 , wherein the sampling circuit is a universal asynchronous receiver/transmitter (UART).

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