Memory system that carries out soft bit decoding

Abstract

A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.

What is claimed is: 
     
         1 . A memory system comprising:
 a nonvolatile semiconductor memory;   a controller configured to
 maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, 
 count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, 
 determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and 
 carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order. 
   
     
     
         2 . The memory system according to  claim 1 , wherein
 the plurality of LLR tables includes a first plurality of LLR tables that is different depending on the number of times of the write operations and the number of times of the erase operations, and a second plurality of LLR tables that is different depending on the number of times of the read operations.   
     
     
         3 . The memory system according to  claim 1 , wherein the unit storage region is a unit of erasing data from the nonvolatile semiconductor memory. 
     
     
         4 . The memory system according to  claim 1 , wherein
 the controller carries out the decoding using a next LLR table in the determined order, when the decoding using the selected LLR table fails.   
     
     
         5 . The memory system according to  claim 1 , wherein
 the data read from the target unit storage region include a plurality of values that are sensed using different read voltages.   
     
     
         6 . A memory system comprising:
 a nonvolatile semiconductor memory;   a controller configured to
 maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, 
 determine an order in which the LLR tables are referred to, based on a physical location of a target unit storage region of a read operation, and 
 carryout decoding of data read from the target unit storage region, using one of the LLR tables selected according to the determined order. 
   
     
     
         7 . The memory system according to  claim 6 , wherein
 the controller determines the order to be a first order when the target unit storage region is located at an end of the storage regions, and to be a second order different from the first order when the target unit storage region is not located at the end of the storage regions.   
     
     
         8 . The memory system according to  claim 7 , wherein the unit storage region is a unit of erasing data from the nonvolatile semiconductor memory. 
     
     
         9 . The memory system according to  claim 6 , wherein
 the controller determines the order to be a first order when the target unit storage region is connected to a first word line, and to be a second order different from the first order when the target unit storage region is connected to a second word line that is located outer than the first word line in a thickness direction of the nonvolatile semiconductor memory.   
     
     
         10 . The memory system according to  claim 6 , wherein the unit storage region is a unit of reading data from the nonvolatile semiconductor memory. 
     
     
         11 . The memory system according to  claim 6 , wherein
 the controller carries out the decoding using a next LLR table in the determined order, when the decoding using the selected LLR table fails.   
     
     
         12 . The memory system according to  claim 6 , wherein
 the controller is further configured to count a number of times decoding of data that are read using each of the LLR tables was successful, with respect to each of the unit storage regions, and determine the order also based on the counted numbers corresponding to the target unit storage region.   
     
     
         13 . The memory system according to  claim 6 , wherein
 the controller selects one of the LLR tables that corresponds to the target unit storage region and of which counted number is the smallest, first.   
     
     
         14 . The memory system according to  claim 6 , wherein
 the data read from the target unit storage region include a plurality of values that are sensed using different read voltages.   
     
     
         15 . A memory system comprising:
 a nonvolatile semiconductor memory;   a controller configured to
 maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, 
 count a number of times decoding of data that are read using each of the LLR tables was successful, 
 determine an order in which the LLR tables are referred to, based on the counted number, and 
 carry out decoding of data read from a target unit storage region of a read operation, using one of the LLR tables selected according to the determined order. 
   
     
     
         16 . The memory system according to  claim 15 , wherein
 the controller selects one of the LLR tables of which counted number is the smallest, first.   
     
     
         17 . The memory system according to  claim 15 , wherein the controller is further configured to
 count a second number of times write and erase operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory,   count the number of times decoding of data that are read using each of the LLR tables was successful with respect to each range of the number of times of the write and erase operations, and   determine the order also based on the second counted number.   
     
     
         18 . The memory system according to  claim 15 , wherein the controller is further configured to
 count a second number of times read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory,   count the number of times decoding of data that are read using each of the LLR tables was successful with respect to each range of the number of times of the write and erase operations, and   determine the order also based on the second counted number.   
     
     
         19 . The memory system according to  claim 15 , wherein
 the controller carries out the decoding using a next LLR table in the determined order, when the decoding using the selected LLR table fails.   
     
     
         20 . The memory system according to  claim 15 , wherein
 the data read from the target unit storage region include a plurality of values that are sensed using different read voltages.