Semiconductor device and system performing calibration operation

Abstract

A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. The calibrations circuit may perform the calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in another semiconductor device.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a calibration circuit configured to perform a calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in a controller; and   an output circuit coupled to the signal transmission line, a resistance value of the output circuit being set based on a result of the calibration operation.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the calibration circuit generates a pull-up code and a pull-down code by being coupled to the reference resistor. 
     
     
         3 . The semiconductor device according to  claim 2 , wherein the output circuit includes a plurality of pull-up resistor legs and a plurality of pull-down resistor legs, and wherein resistance values of the plurality of pull-up resistor legs are set based on the pull-up code, and resistance values of the plurality of pull-down resistor legs are set based on the pull-down code. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the reference resistor is provided in an output circuit of another semiconductor device that is coupled to the signal transmission line. 
     
     
         5 . A semiconductor system comprising:
 a first semiconductor device including an output circuit coupled to a signal transmission line; and   a second semiconductor device including:   an output circuit coupled with the signal transmission line; and   a calibration circuit configured to perform a calibration operation by being coupled, through the signal transmission line, to a reference resistor provided in the first semiconductor device,   wherein a resistance value of the output circuit of the second semiconductor device is set based on a result of the calibration operation.   
     
     
         6 . The semiconductor system according to  claim 5 , wherein the first semiconductor device further includes a calibration circuit generating a first pull-up code and a first pull-down code by being coupled to an external reference resistor. 
     
     
         7 . The semiconductor system according to  claim 6 , wherein the output circuit of the first semiconductor device includes a plurality of pull-up resistor legs and a plurality of pull-down resistor legs, and wherein resistance values of the plurality of pull-up resistor legs are set based on the first pull-up code, and resistance values of the plurality of pull-down resistor legs are set based on the first pull-down code. 
     
     
         8 . The semiconductor system according to  claim 7 , wherein the first semiconductor device turns on at least one of the plurality of pull-up resistor legs and the plurality of pull-down resistor legs based on a calibration select signal, and the turned-on resistor leg is coupled to the signal transmission line. 
     
     
         9 . The semiconductor system according to  claim 5 , wherein the calibration circuit of the second semiconductor device generates a second pull-up code and a second pull-down code by being coupled to the reference resistor. 
     
     
         10 . The semiconductor system according to  claim 9 , wherein the output circuit of the second semiconductor device includes a plurality of pull-up resistor legs and a plurality of pull-down resistor legs, and wherein resistance values of the plurality of pull-up resistor legs are set based on the second pull-up code, and resistance values of the plurality of pull-down resistor legs are set based on the second pull-down code. 
     
     
         11 . A semiconductor system comprising:
 a first semiconductor device coupled to a signal transmission line, and including an output circuit that includes a plurality of pull-up resistor legs and a plurality of pull-down resistor legs; and   a second semiconductor device including:   an output circuit coupled to the signal transmission line, and including a plurality of pull-up resistor legs and a plurality of pull-down resistor legs; and   a calibration circuit coupled to the signal transmission line, and configured to perform a calibration operation to set resistance values of the plurality of pull-up resistor legs and the plurality of pull-down resistor legs of the output circuit of the second semiconductor device.   
     
     
         12 . The semiconductor system according to  claim 11 , wherein the first semiconductor device further includes a calibration circuit generating a first pull-up code and a first pull-down code by being coupled to an external reference resistor. 
     
     
         13 . The semiconductor system according to  claim 12 , wherein resistance values of the plurality of pull-up resistor legs of the output circuit of the first semiconductor device are set based on the first pull-up code, and resistance values of the plurality of pull-down resistor legs of the output circuit of the first semiconductor device are set based on the first pull-down code. 
     
     
         14 . The semiconductor system according to  claim 12 , wherein the first semiconductor device turns on at least one of the plurality of pull-up resistor legs and the plurality of pull-down resistor legs of the output circuit of the first semiconductor device based on a first calibration select signal, and the turned-on resistor leg is coupled to the signal transmission line. 
     
     
         15 . The semiconductor system according to  claim 14 , wherein the second semiconductor device turns on at least one of the plurality of pull-up resistor legs and the plurality of pull-down resistor legs of the output circuit of the second semiconductor device based on a second calibration select signal, and the turned-on resistor leg is coupled to the signal transmission line. 
     
     
         16 . The semiconductor system according to  claim 15 , wherein the calibration circuit of the second semiconductor device generates a second pull-up code and a second pull-down code by being coupled to the signal transmission line. 
     
     
         17 . The semiconductor system according to  claim 16 , wherein resistance values of the plurality of pull-up resistor legs of the output circuit of the second semiconductor device are set based on the second pull-up code, and resistance values of the plurality of pull-down resistor legs of the output circuit of the second semiconductor device are set based on the second pull-down code. 
     
     
         18 . A method of operating a semiconductor system including a controller and a memory device coupled to each other through a signal transmission line, the method comprising:
 performing a calibration operation of the controller by being coupled to an external reference resistor;   setting a resistance value of a controller output circuit coupled to the signal transmission line, based on a result of the calibration operation of the controller;   performing a calibration operation of the memory device by being coupled to the controller output circuit through the signal transmission line and by being coupled to a reference resistor provided from the controller output circuit; and   setting a resistance value of a memory output circuit coupled to the signal transmission line, based on a result of the calibration operation of the memory device.   
     
     
         19 . The method according to  claim 18 , wherein the controller output circuit includes a plurality of pull-up resistor legs and a plurality of pull-down resistor legs, and wherein the method further comprises, before performing the calibration operation of the memory device, coupling at least one of the plurality of pull-up resistor legs and the plurality of pull-down resistor legs of the controller output circuit, to the signal transmission line. 
     
     
         20 . The method according to  claim 19 , wherein the memory circuit includes a plurality of pull-up resistor legs and a plurality of pull-down resistor legs, and wherein the method further comprises, before performing the calibration operation of the memory device, coupling at least one of the plurality of pull-up resistor legs and the plurality of pull-down resistor legs of the memory output circuit, to the signal transmission line. 
     
     
         21 . A semiconductor system comprising:
 a controller coupled to first and second signal transmission lines;   a first memory device coupled to the first and second signal transmission lines, and including a first memory calibration circuit; and   a second memory device coupled to the first and second signal transmission lines, and including a second memory calibration circuit,   wherein the first memory calibration circuit performs a calibration operation by being coupled to the first signal transmission line based on a first chip calibration select signal, and the second memory calibration circuit performs a calibration operation by being coupled to the second signal transmission line based on a second chip calibration select signal.   
     
     
         22 . The semiconductor system according to  claim 21 , wherein the first memory calibration circuit and the second memory calibration circuit perform the impedance calibration operations simultaneously. 
     
     
         23 . The semiconductor system according to  claim 21 , wherein the controller comprises:
 a controller calibration circuit configured to perform a calibration operation by being coupled to an external reference resistor;   a first controller output circuit coupled to the first signal transmission line, a resistance value of the first controller output circuit being set by the controller calibration circuit; and   a second controller output circuit coupled to the second signal transmission line, a resistance value of the second controller output circuit being set by the controller calibration circuit.   
     
     
         24 . The semiconductor system according to  claim 23 , wherein the first memory device further includes:
 a first memory output circuit coupled to the first signal transmission line, a resistance value of the first memory output circuit being set by the first memory calibration circuit; and   a second memory output circuit coupled to the second signal transmission line, a resistance value of the second memory output circuit being set by the first memory calibration circuit.   
     
     
         25 . The semiconductor system according to  claim 24 , wherein the first memory output circuit includes a plurality of pull-up resistor legs and a plurality of pull-down resistor legs both coupled to the first signal transmission line, and the second memory output circuit includes a plurality of pull-up resistor legs and a plurality of pull-down resistor legs both coupled to the second signal transmission line, and wherein at least one of the pluralities of resistor legs of the first memory output circuit is turned on based on the first chip calibration select signal, and all of the pluralities of resistor legs of the second memory output circuit are turned off based on the second chip calibration select signal. 
     
     
         26 . The semiconductor system according to  claim 23 , wherein the second memory device further includes:
 a third memory output circuit coupled to the first signal transmission line, a resistance value of the third memory output circuit being set by the second memory calibration circuit; and   a fourth memory output circuit coupled to the second signal transmission line, a resistance value of the fourth memory output circuit being set by the second memory calibration circuit.   
     
     
         27 . The semiconductor system according to  claim 26 , wherein the third memory output circuit includes a plurality of pull-up resistor legs and a plurality of pull-down resistor legs both coupled to the first signal transmission line, and the fourth memory output circuit includes a plurality of pull-up resistor legs and a plurality of pull-down resistor legs both coupled to the second signal transmission line, and wherein all of the pluralities of resistor legs of the third memory output circuit are turned off based on the first chip calibration select signal, and at least one of the pluralities of resistor legs of the fourth memory output circuit is turned on based on the second chip calibration select signal. 
     
     
         28 . A semiconductor system comprising:
 a controller including a controller calibration circuit configured to perform a calibration operation by being coupled to an external reference resistor; and   a memory device including a memory calibration circuit configured to perform a calibration operation by being coupled to the external reference resistor.   
     
     
         29 . The semiconductor system according to  claim 28 , wherein the controller further includes a controller output circuit coupled to a signal transmission line, and wherein a resistance value of the controller output circuit is set based on a result of the calibration operation of the controller calibration circuit. 
     
     
         30 . The semiconductor system according to  claim 29 , wherein the memory device further includes a memory output circuit coupled to the signal transmission line, and wherein a resistance value of the memory output circuit is set based on a result of the calibration operation of the memory calibration circuit. 
     
     
         31 . The semiconductor system according to  claim 28 , wherein the controller calibration circuit is coupled to the external reference resistor based on a first calibration signal, the memory calibration circuit is coupled to the external reference resistor based on a second calibration signal, and enable periods of the first and second calibration signals do not overlap each other.