Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device having a high degree of freedom of layout has a first part AR 1 , in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP 2 ) for the plurality of wells PW is arranged on one side so as to interpose the AR 1 in a Y-axis direction, and a common power feeding region (ARN 2 ) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP 2 ) for the PW wells, a p + -type power-feeding diffusion layer P+ (DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR 1 , and a plurality of MIS transistors are correspondingly formed.

1 . A semiconductor device comprising:
 a first well region of a first conductivity type including first, second and third parts;   a first power feeding region of the first conductivity type; and   a second well region of a second conductivity type including a fourth part,   wherein the first part is arranged next to the fourth part,   wherein the second part is arranged next to the fourth part,   wherein the fourth part is arranged between the first part and the second part in a first direction,   the third part has a shape extending in the first direction, and is arranged to be connected to the first part and the second part and be next to the fourth part in a second direction intersecting with the first direction,   the first power feeding region supplies a predetermined potential to the first part and the second part via the first well region.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the first power feeding region extend along the fourth part in the first direction.   
     
     
         3 . The semiconductor device according to  claim 1 , further comprising:
 a first gate layer extending in the first direction so as to cross a boundary between the first part and the fourth part or a boundary between the fourth part and the second part;   a first semiconductor region of the second conductivity type formed in the first part or the second part to be a source/drain region of a MIS transistor using the first gate layer as a gate; and   a second semiconductor region of the first conductivity type formed in the fourth part to be a source/drain region of a MIS transistor using the first gate layer as a gate.   
     
     
         4 . The semiconductor device according to  claim 3 , further comprising:
 a dummy gate layer extending along the first gate layer and arranged between the first gate layer and the first power feeding region in the second direction,   wherein the dummy gate layer does not include a semiconductor region to be a source or a drain on the first power feeding region side.   
     
     
         5 . The semiconductor device according to  claim 1 , further comprising:
 a memory array including a word line extending in the first direction, a plurality of bit lines extending in the second direction, and a plurality of memory cells arranged at intersection points between the word line and the plurality of bit lines; and   a column control circuit which inputs and outputs a signal to/from the plurality of bit lines,   wherein agate layer of a MIS transistor included in each of the plurality of memory cells extends in the first direction, and   
       a part of the column control circuit is formed in the first well region and the second well region. 
     
     
         6 . The semiconductor device according to  claim 5 ,
 wherein, in the first well region and the second well region, an input buffer circuit into which external input data to be applied to the plurality of bit lines is taken and an output buffer circuit from which a signal read from the plurality of bit lines is outputted as external output data are formed.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein the semiconductor device includes a plurality of first unit regions sequentially arranged in the first direction,   each of the plurality of first unit regions includes the first well region including the first part to the third part, the first power feeding region, and the second well region including the fourth part, and   the third parts of the first well regions included in the plurality of first unit regions are joined to each other so as to cross the plurality of first unit regions.   
     
     
         8 . The semiconductor device according to  claim 1 , further comprising:
 a second power feeding region of the second conductivity type,   wherein the second well region further includes:
 a fifth part arranged to be opposed to the fourth part so as to interpose the second part there between in the first direction; and 
 a sixth part having a shape extending in the first direction and arranged to be joined to the fourth part and the fifth part and be next to the second part on a side opposed to the third part so as to interpose the fourth, second, and fifth parts therebetween in the second direction, 
 the second power feeding region is supplies a predetermined potential to the fourth part and the fifth part via the second well region, and 
 the second power feeding region includes a first region arranged to be opposite to a whole or a part of the first part and a second region arranged to be opposite to a whole or a part of the second part in the second direction. 
   
     
     
         9 . The semiconductor device according to  claim 8 , further comprising:
 a second gate layer extending in the first direction so as to cross a boundary between the first part and the fourth part, a boundary between the fourth part and the second part, or a boundary between the second part and the fifth part;
 a third semiconductor region of the second conductivity type formed in the first part or the second part to be a source/drain region of a MIS transistor using the second gate layer as a gate; and 
 a fourth semiconductor region of the first conductivity type formed in the fourth part or the fifth part to be a source/drain region of a MIS transistor using the second gate layer as a gate. 
   
     
     
         10 . The semiconductor device according to  claim 8 ,
 wherein the semiconductor device includes a plurality of second unit regions sequentially arranged in the first direction,   each of the plurality of second unit regions includes the first well region including the first part to the third part, the first power feeding region, the second well region including the fourth part to the sixth part, and the second power feeding region, and   the third parts of the first well regions included in the plurality of respective second unit regions are joined to each other so as to cross the plurality of second unit regions.   
     
     
         11 . The semiconductor device according to  claim 1 ,
 wherein a size of the first power feeding region in the first direction is larger than a size of the first power feeding region in the second direction.