Method and system for fabricating unique chips using a charged particle multi-beamlet lithography system

Abstract

A method of creating electronic devices such as semiconductor chips using a maskless lithographic exposure system such as a charged particle multi-beamlet lithography system ( 301 A- 301 D). The maskless lithographic exposure system comprises a lithography subsystem ( 316 ) including a maskless pattern writer such as a charged particle multi-beamlet lithography machine ( 1 ) or ebeam machine. The method comprises introducing unique chip design data ( 430 ) or information related thereto into pattern data comprising common chip design data before streaming the pattern data to the maskless pattern writer.

1 . A method of creating electronic devices using a maskless lithographic exposure system comprising maskless pattern writer,
 the method comprising introducing unique chip design data or information related thereto into pattern data comprising common chip design data before streaming the pattern data to the maskless pattern writer.   
     
     
         2 . The method according to  claim 1 ,
 wherein the maskless lithographic exposure system further comprises a data processing system,   wherein the pattern writer is controlled by the data processing system,   wherein the data processing system is adapted to be fed by software data relating to a pattern to be transferred to a target in which the electronics devices are to be effected,   wherein provision of the patterning data to the pattern writer by said data processing system is realized on the basis of said pattern data fed to the exposure system,   the method comprising:   feeding a common part of the pattern data for electronics devices to be effected on the target at a first data entry of the data processing system, in particular at an instance thereof related to processing pattern data per target; and   feeding unique pattern data or information at a second data entry of the data processing system at an instance thereof downstream the data flow in the data processing system relative to the first data entry, in particular capable of processing pattern data per part of the target.   
     
     
         3 - 5 . (canceled) 
     
     
         6 . A method of processing a wafer, wherein, at manufacture of the wafer, a first part of the wafer is exposed for creating an identical part of a chip which is identical to other chips created on the wafer, wherein a second part of the wafer is exposed for creating a unique part of said chip which is different from other chips created on the wafer. 
     
     
         7 . (canceled) 
     
     
         8 . The method according to  claim 6 , wherein the second part of the wafer is exposed using beamlets that are controlled using pattern data comprising a common chip design part that is reusable with other chips and a unique chip design part that is unique for the chip. 
     
     
         9 - 12 . (canceled) 
     
     
         13 . The method according to  claim 6 , wherein the first part and the second part of the wafer are exposed using electron beam exposure. 
     
     
         14 - 15 . (canceled) 
     
     
         16 . A maskless lithographic exposure system comprising a maskless pattern writer,
 wherein the maskless lithographic exposure system is configured to expose a pattern on a surface of a target according to pattern data,   wherein the pattern data comprises common chip design data, the common chip design data describing a chip layout design applicable to multiple chips, and   wherein the maskless lithographic exposure system is configured to insert unique chip design data into the pattern data before streaming the pattern data to the maskless pattern writer.   
     
     
         17 . (canceled) 
     
     
         18 . The maskless lithographic exposure system according to  claim 16 , comprising a pattern data processing system configured to pre-process a vector based input design file used for generating the pattern data comprising the common chip design data, and a pattern streamer configured to receive the pattern data comprising the common chip design data and to insert the unique chip design data into the pattern data. 
     
     
         19 . The maskless lithographic exposure system according to  claim 16 , comprising a pattern streamer configured to stream the pattern data comprising the common chip design data to the lithography subsystem, and wherein the lithography subsystem is configured to insert the unique chip design data into the pattern data. 
     
     
         20 - 21 . (canceled) 
     
     
         22 . The maskless lithographic exposure system according to  claim 16 , further comprising a unique data generator for generating the unique chip design data based on secret data. 
     
     
         23 . The maskless lithographic exposure system according to  claim 22 , wherein the unique data generator is configured to receive the secret data from an external provider in an encrypted format. 
     
     
         24 . The maskless lithographic exposure system according to  claim 16 , wherein the common chip design data describes at least a portion of a chip layout design applicable for a plurality of chips, wherein the common chip design data includes design data describing at least one of a plurality of electrical circuit elements and a plurality of connections between electrical circuit elements, for at least one layer of the chip layout. 
     
     
         25 . The maskless lithographic exposure system according to  claim 24 , wherein the unique chip design data describes at least a portion of a chip layout design applicable for a single chip of the plurality of chips, wherein the unique chip design data includes design data describing at least one of a plurality of electrical circuit elements and a plurality of connections between electrical circuit elements, for at least one layer of the chip layout. 
     
     
         26 . The maskless lithographic exposure system according to  claim 25 , wherein the unique chip design data includes design data describing at least one of a plurality of electrical circuit elements and a plurality of connections between electrical circuit elements, for only one layer of the chip layout. 
     
     
         27 . The maskless lithographic exposure system according to  claim 25 , wherein the unique chip design data includes design data describing via connections between two or more layers of the chip layout. 
     
     
         28 . The maskless lithographic exposure system according to  claim 25 , wherein the unique chip design data includes design data describing active regions of electrical circuit elements of the chip layout. 
     
     
         29 . A lithography system configured to perform a method of processing a wafer, wherein, at manufacture of the wafer, a first part of the wafer is exposed for creating an identical part of a chip which is identical to other chips created on the wafer, wherein a second part of the wafer is exposed for creating a unique part of said chip which is different from other chips created on the wafer. 
     
     
         30 . An electronic device, created using a maskless lithographic exposure system comprising a maskless pattern writer,
 wherein the maskless lithographic exposure system is configured to expose a pattern on a surface of a target according to pattern data,   wherein the pattern data comprises common chip design data, the common chip design data describing a chip layout design applicable to multiple chips, and   wherein the maskless lithographic exposure system is configured to insert unique chip design data into the pattern data before streaming the pattern data to the maskless pattern writer.   
     
     
         31 . The electronic device according to  claim 30 , wherein the electronic device is a truly unique semiconductor chip different from any other created semiconductor chip. 
     
     
         32 . An electronic device, which is a member of a set of semiconductor chips, comprising:
 a common design layout part which is the same for all of the semiconductor chips of the set; and   a non-common design layout part which is the same for only a subset of the semiconductor chips of the set and is different for other ones of the semiconductor chips of the set,   wherein the non-common design layout part is created using a maskless lithographic exposure system based on secret data provided to the maskless lithographic exposure system during creation of the non-common design layout part.   
     
     
         33 . An electronic device, which is a member of a set of semiconductor chips, the semiconductor chip comprising a common design layout part and a non-common design layout part formed in three or more layers of the semiconductor chip comprising:
 a common design layout part which is the same for all of the semiconductor chips of the set; and   a non-common design layout part which is the same for only a subset of the semiconductor chips of the set,   wherein the non-common design layout part is formed on at least a first one of the layers having a second one of the layers above the first layer and having a third one of the layers below the first layer.   
     
     
         34 . An electronic device, which is a member of a set of semiconductor chips, the semiconductor chip comprising a common design layout part and a non-common design layout part formed in a plurality of layers of the semiconductor chip comprising:
 a common design layout part which is the same for all of the semiconductor chips of the set; and   a non-common design layout part which is the same for only a subset of the semiconductor chips of the set,   wherein the non-common design layout part includes at least one of: connections between metal layers of the plurality of layers; connections between a metal layer and a gate in a contact layer of the plurality of layers; connections in a local interconnect layer of the plurality of layers; and a P- or N-doped active region of a transistor or diode of one of the plurality of layers.   
     
     
         35 . The electronic device according to  claim 33 , wherein the common design layout part and the non-common design layout part are interconnected to form an electronic circuit. 
     
     
         36 . The electronic device according to  claim 35 , wherein the electronic device comprises at least one input terminal for receiving a challenge and at least one output terminal for outputting a response, and the electronic circuit forms a challenge-response circuit connected to the at least one input terminal and the at least one output terminal,
 wherein the challenge-response circuit is adapted for generating a response at the at least one output terminal based on a challenge applied to the at least one input terminal, the challenge and the response having a predetermined relationship.   
     
     
         37 . (canceled) 
     
     
         38 . A computer-implemented method for generating pattern data,
 wherein the pattern data represents at least a part of one or more electronic devices, to be created under control of the pattern data using a maskless lithographic exposure system comprising a maskless pattern writer,   the method comprising inserting non-common chip design data or information related thereto into common chip design data to obtain the pattern data before streaming the pattern data to the maskless pattern writer.   
     
     
         39 . The method according to  claim 38 ,
 wherein the common chip design data defines a common design layout part of an electronic device to be created on a wafer using the maskless pattern writer under control of the pattern data, the common design layout part being identical to other electronic devices created on the wafer,   and wherein the non-common chip design data defines a non-common design layout part of said electronic device to be created on the wafer using the maskless pattern writer under control of the pattern data, the non-common design layout part being different from other chips created on the wafer.   
     
     
         40 . The method according to  claim 38 ,
 wherein the common design layout part is the same for all electronic devices of a set of electronic devices,   and wherein the non-common design layout part is the same for only a subset of the electronic devices of the set and is different for other ones of the electronic devices of the set.   
     
     
         41 . A data processing system comprising a processor configured to perform a computer-implemented method for generating pattern data,
 wherein the pattern data represents at least a part of one or more electronic devices, to be created under control of the pattern data using a maskless lithographic exposure system comprising a maskless pattern writer,   the method comprising inserting non-common chip design data or information related thereto into common chip design data to obtain the pattern data before streaming the pattern data to the maskless pattern writer.   
     
     
         42 . A computer-implemented method for generating non-common chip design data, the method comprising:
 receiving secret data from an external provider;   generating the non-common chip design data based on the secret data, wherein the non-common chip design data defines a non-common design layout part of an electronic device to be created on a wafer using a maskless pattern writer, the non-common design layout part being different from other chips created on the wafer.   
     
     
         43 . The method according to  claim 42  further comprising:
 receiving product identification information or serial number information related to a chip to be manufactured from a manufacturing database; 
 receiving batches of identification/key pairs from a key management service; 
 controlling the generation of the non-common chip design data using the received product identification information or serial number information and the received identification/key pairs. 
 
     
     
         44 . A data processing system comprising a processor configured to perform a computer-implemented method for generating non-common chip design data, the method comprising:
 receiving secret data from an external provider;   generating the non-common chip design data based on the secret data, wherein the non-common chip design data defines a non-common design layout part of an electronic device to be created on a wafer using a maskless pattern writer, the non-common design layout part being different from other chips created on the wafer.   
     
     
         45 . A computer program product, implemented on computer-readable non-transitory storage medium, comprising instructions which, when the computer program product is executed by a computer, cause the computer to carry out a computer-implemented method for generating non-common chip design data, the method comprising:
 receiving secret data from an external provider;   generating the non-common chip design data based on the secret data, wherein the non-common chip design data defines a non-common design layout part of an electronic device to be created on a wafer using a maskless pattern writer, the non-common design layout part being different from other chips created on the wafer.   
     
     
         46 . A computer-readable non-transitory storage medium comprising instructions which, when executed by a computer, cause the computer to carry out a computer-implemented method for generating non-common chip design data, the method comprising:
 receiving secret data from an external provider;   generating the non-common chip design data based on the secret data, wherein the non-common chip design data defines a non-common design layout part of an electronic device to be created on a wafer using a maskless pattern writer, the non-common design layout part being different from other chips created on the wafer.