US2018063362A1PendingUtilityA1

Serial data transfer using transfer type information to select a storage unit

Assignee: TOSHIBA KKPriority: Jul 10, 2015Filed: Nov 6, 2017Published: Mar 1, 2018
Est. expiryJul 10, 2035(~8.9 yrs left)· nominal 20-yr term from priority
Inventors:Shigeru Morino
H03M 7/14H04N 2201/0094H04N 1/2158G06F 13/4291G06F 13/00
45
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A serial data transfer apparatus includes a decoder, a counter, and a calculation circuit. The decoder is configured to decode serial data to obtain written data, a base address, and transfer type information for specifying a storage unit for storing the written data. The counter is configured to count a frame synchronization pulse. The calculation circuit is configured to generate a chip select signal based on the transfer type information and the base address, as decoded by the decoder, and a count value of the frame synchronization pulse output by the counter.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A serial data transfer apparatus, comprising:
 a determination circuit configured to determine transfer type information according to information in serial data;   a writing circuit configured to write a base address read from the serial data in response to the transfer type being burst access;   a counting circuit configured to count a frame synchronization pulse during the burst access;   a reading circuit configured to read a count value from the counting circuit;   a selecting circuit configured to select a storage unit of a plurality of storage units based on the transfer type;   an output circuit configured to output a chip select signal to the selected storage unit; and   a holding circuit configured to hold data to be written to the selected storage unit.   
     
     
         2 . The apparatus according to  claim 1 ,
 wherein the transfer type information indicates an order of the plurality of storage units in which to store the written data.   
     
     
         3 . The apparatus according to  claim 2 ,
 wherein the output circuit is configured to sequentially output the chip select signal to adjacent storage units of the plurality of storage units based on the transfer type information.   
     
     
         4 . The apparatus according to  claim 2 ,
 wherein the output circuit is configured to output the chip select signal to a storage unit of every two adjacent storage units of the plurality of storage units based on the transfer type information.   
     
     
         5 . The apparatus according to  claim 1 ,
 wherein the transfer type information further includes access information for determining whether to perform burst access or direct access.   
     
     
         6 . The apparatus according to  claim 5 ,
 wherein the writing circuit is configured to set a flag bit to a storage unit in response to the access information representing the burst access.   
     
     
         7 . The apparatus according to  claim 6 ,
 wherein the serial data includes a burst access threshold value representing a total number of accesses to the storage unit, and   wherein the apparatus further comprises a controller configured to reset the flag bit in response to the number of accesses to the storage unit exceeding the burst access threshold value.   
     
     
         8 . A serial data transfer method, comprising:
 determining transfer type information according to information in serial data;   writing a base address read from the serial data in response to the transfer type being burst access;   counting a frame synchronization pulse during the burst access;   reading a count value from the counting circuit;   selecting a storage unit of a plurality of storage units based on the transfer type;   outputting a chip select signal to the selected storage unit; and   holding data to be written to the selected storage unit.   
     
     
         9 . The method according to  claim 8 ,
 wherein the transfer type information indicates an order of the plurality of storage units in which to store the written data.   
     
     
         10 . The method according to  claim 9 ,
 further comprising sequentially outputting the chip select signal to adjacent storage units of the plurality of storage units based on the transfer type information.   
     
     
         11 . The method according to  claim 9 ,
 further comprising outputting the chip select signal to a storage unit of every two adjacent storage units of the plurality of storage units based on the transfer type information.   
     
     
         12 . The method according to  claim 8 ,
 wherein the transfer type information further includes access information for determining whether to perform burst access or direct access.   
     
     
         13 . An image formation apparatus, comprising:
 an engine configured to read image data of an original document; and   a serial data transfer apparatus configured to write the image data in a storage unit,   wherein the serial data transfer apparatus includes:
 a determination circuit configured to determine transfer type information according to information in serial data; 
 a writing circuit configured to write a base address read from the serial data in response to the transfer type being burst access; 
 a counting circuit configured to count a frame synchronization pulse during the burst access; 
 a reading circuit configured to read a count value from the counting circuit; 
 a selecting circuit configured to select the storage unit of a plurality of storage units based on the transfer type; 
 an output circuit configured to output a chip select signal to the selected storage unit; and 
 a holding circuit configured to hold data to be written to the selected storage unit. 
   
     
     
         14 . The image formation apparatus according to  claim 13 ,
 wherein the transfer type information indicates an order of the plurality of storage units in which to store the written data.   
     
     
         15 . The image formation apparatus according to  claim 14 ,
 wherein the output circuit is configured to sequentially output the chip select signal to adjacent storage units of the plurality of storage units based on the transfer type information.   
     
     
         16 . The apparatus according to  claim 14 ,
 wherein the output circuit is configured to output the chip select signal to a storage unit of every two adjacent storage units of the plurality of storage units based on the transfer type information.   
     
     
         17 . The apparatus according to  claim 13 ,
 wherein the transfer type information further includes access information for determining whether to perform burst access or direct access.   
     
     
         18 . The apparatus according to  claim 17 ,
 wherein the writing circuit is configured to set a flag bit to a storage unit in response to the access information representing the burst access.   
     
     
         19 . The apparatus according to  claim 18 ,
 wherein the serial data includes a burst access threshold value representing a total number of accesses to the storage unit, and   wherein the apparatus further comprises a controller configured to reset the flag bit in response to the number of accesses to the storage unit exceeding the burst access threshold value.

Join the waitlist — get patent alerts

Track US2018063362A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.