Semiconductor Device with a Source Trench Electrode

Abstract

A semiconductor device includes a body region arranged between source and drift regions in a semiconductor body. A gate trench extends from a first surface of the semiconductor body, through the source and body regions and into the drift region. A diode region extends under the gate trench, and a pn junction is between the diode region and the drift region below the gate trench. A gate electrode arranged in the gate trench is dielectrically insulated from the source, body, diode and drift regions by a gate dielectric. A further trench spaced apart from the gate trench extends from the first surface of the semiconductor body, through the source and diode regions and into the drift region. A source electrode arranged in the further trench adjoins the drift region in the further trench to form a Schottky contact with the drift region.

What is claimed is: 
     
         1 . A semiconductor device, comprising a semiconductor body and at least one device cell integrated in the semiconductor body, the at least one device cell comprising:
 a drift region, a source region, and a body region arranged between the source region and the drift region;   a gate trench extending from a first surface of the semiconductor body, through the source region and the body region and into the drift region;   a diode region extending under the gate trench;   a pn junction between the diode region and the drift region below the gate trench;   a gate electrode arranged in the gate trench and dielectrically insulated from the source region, the body region, the diode region and the drift region by a gate dielectric;   a further trench spaced apart from the gate trench and extending from the first surface of the semiconductor body, through the source region and the diode region and into the drift region; and   a source electrode arranged in the further trench and adjoining the drift region in the further trench to form a Schottky contact with the drift region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the source electrode in the further trench adjoins the source region. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the further trench comprises a first sidewall, a second sidewall opposite the first sidewall, and a bottom, wherein the source region adjoins the first and second sidewalls of the further trench and the diode region adjoins at least the first sidewall of the further trench. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a vertical distance between the first surface and a bottom of the further trench is smaller than a vertical distance between the first surface and a lower end of the diode region. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the diode region comprises a lower diode region arranged below a bottom of the gate trench, wherein the lower diode region has a maximum of a doping concentration distant to the bottom of the gate trench, and wherein a distance between the bottom of the gate trench and a position of the maximum of the doping concentration is between 200 nanometers and 1 micrometer. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the diode region further comprises a local minimum of the doping concentration between the position of the maximum doping concentration and the bottom of the gate trench. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the gate trench comprises a first sidewall adjoining the body region, a second sidewall adjoining the diode region, and a bottom adjoining the pn junction. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the gate dielectric has a first thickness at the first sidewall of the gate trench and a second thickness at the second sidewall of the gate trench, and wherein the second thickness is greater than the first thickness. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the second thickness is at least 1.5 times the first thickness. 
     
     
         10 . The semiconductor device of  claim 8 , wherein the gate dielectric has a third thickness at the bottom of the trench, wherein the third thickness is greater than the first thickness. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the third thickness is at least 1.5 times the first thickness. 
     
     
         12 . The semiconductor device of  claim 7 , wherein the gate trench comprises a rounded corner between the first sidewall and the bottom, and wherein a radius of the rounded corner is at least 2 times a thickness of the gate dielectric at the first sidewall. 
     
     
         13 . The semiconductor device of  claim 1 , wherein the diode region comprises:
 a first diode region forming the pn-junction with the drift region; and   a second diode region more highly doped than the first diode region and connected to the source electrode.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the second diode region adjoins a sidewall of the gate trench. 
     
     
         15 . The semiconductor device of  claim 14 , wherein the diode region comprises a third diode region more highly doped than the second diode region, wherein the third diode region adjoins the same sidewall of the gate trench as the second diode region. 
     
     
         16 . The semiconductor device of  claim 1 , wherein the semiconductor body comprises an SiC crystal, and wherein a sidewall of the gate trench is aligned with a c-axis of the SiC crystal. 
     
     
         17 . The semiconductor device of  claim 1 , wherein the source electrode in the further trench adjoins the diode region. 
     
     
         18 . A method of producing a semiconductor device, the method comprising:
 forming a drift region, a source region, and a body region arranged between the source region and the drift region in a semiconductor body;   forming a gate trench extending from a first surface of the semiconductor body, through the source region and the body region and into the drift region;   forming a diode region extending under the gate trench, wherein a pn junction is formed between the diode region and the drift region below the gate trench;   forming a gate electrode in the gate trench and dielectrically insulated from the source region, the body region, the diode region and the drift region by a gate dielectric;   forming a further trench spaced apart from the gate trench and extending from the first surface of the semiconductor body, through the source region and the diode region and into the drift region; and   forming a source electrode in the further trench and adjoining the drift region in the further trench to form a Schottky contact with the drift region.   
     
     
         19 . The method of  claim 18 , further comprising:
 prior to forming the further trench, forming an insulation layer on the first surface;   forming a contact opening in the insulation layer above the gate electrode; and   forming a gate connection electrode that is electrically connected to the gate electrode in the contact opening.   
     
     
         20 . The method of  claim 18 , further comprising:
 after forming the gate trench, subjecting the semiconductor body to a thermal treatment in a hydrogen atmosphere.