Semiconductor device and electronic device

Abstract

A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.

1 - 13 . (canceled) 
     
     
         14 . A semiconductor device comprising:
 a first and a second semiconductor chip, each of the first and second semiconductor chips being configured to be coupled to respective first and second external memories, and each of the first and second semiconductor chips including:   (a) a first memory interface configured to be coupled to a corresponding first external memory;   (b) a second memory interface configured to be coupled to a corresponding second external memory;   (c) a first memory controller coupled to the first memory interface such that a first control signal sent from the first memory controller passes through the first memory interface before reaching the first and second external memories;   (d) a second memory controller coupled to the second memory interface such that a second control signal sent from the second memory controller passes through the second memory interface before reaching the second external memory;   (e) an inter-device interface being configured to establish communication between the first semiconductor chip and the second semiconductor chip;   (f) terminals configured to output the second control signal that has passed through the second memory interface; and   (g) a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals,   wherein the first semiconductor chip is configured to access, through the inter-device interfaces of the first and second semiconductor chips, at least one of the first and second external memories coupled to the second semiconductor chip.   
     
     
         15 . The semiconductor device according to  claim 14 , wherein the first semiconductor chip further comprises a second selector, different from the first selector, configured to, in accordance with the operation mode, select between the first control signal output by the first memory controller of the first semiconductor chip and the second control signal output by the second memory controller of the first semiconductor chip and to input the selected control signal to the second memory interface of the first semiconductor chip. 
     
     
         16 . The semiconductor device according to  claim 14 , further comprising a mode terminal for setting the operation mode. 
     
     
         17 . The semiconductor device according to  claim 16 , further comprising a decoder configured to decode a value which is set to the mode terminal. 
     
     
         18 . The semiconductor device according to  claim 15 , wherein when the operation mode is a mode in which the first semiconductor chip communicates with the second semiconductor chip, the first selector of the first semiconductor chip selects the inter-device interface of the first semiconductor chip, and the second selector selects the first control signal. 
     
     
         19 . The semiconductor device according to  claim 15 , wherein when the operation mode is a mode in which the first semiconductor chip is used singly, the first selector of the first semiconductor chip selects the second memory interface of the first semiconductor chip, and the second selector selects the second control signal. 
     
     
         20 . The semiconductor device according to  claim 14 , wherein the first semiconductor chip further includes an internal bus to which the first memory controller, the second memory controller and the inter-device interface are connected. 
     
     
         21 . The semiconductor device according to  claim 14 , wherein the first selector is connected to the terminals at one end and is selectively connected to the second memory interface and the inter-device interface at another end. 
     
     
         22 . The semiconductor device according to  claim 15 , wherein the second selector is connected to the second memory interface at one end and is selectively connected to the first memory controller and the second memory controller at another end. 
     
     
         23 . An electronic device comprising:
 (a) a first semiconductor chip;   (b) a second semiconductor chip configured to communicate with the first semiconductor chip;   (c) a first and second memory coupled to the first semiconductor chip; and   (d) a first and second memory coupled to the second semiconductor chip,   wherein each of the first and second semiconductor chips comprises:
 (i) a first memory interface coupled to the first memory; 
 (ii) a second memory interface coupled to the second memory; 
 (iii) a first memory controller coupled to the first memory interface such that a first control signal output from the first memory controller passes through the first memory interface before reaching the first and second memories; 
 (iv) a second memory controller coupled to the second memory interface such that a second control signal output from the second memory controller passes through the second memory interface before reaching the second memory; 
 (v) an inter-device interface for establishing communication between the first and second semiconductor chips; 
 (vi) terminals configured to output the second control signal that has passed through the second memory interface; and 
 (vii) a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode and to couple the selected interface to the terminals, 
   wherein the first semiconductor chip is configured to access, through the inter-device interfaces, one or more of the first and second memories coupled to the second semiconductor chip.   
     
     
         24 . The electronic device according to  claim 23 , wherein the first semiconductor chip further comprises a second selector, different from the first selector, configured to, in accordance with the operation mode, select between the first control signal output by the first memory controller of the first semiconductor chip and the second control signal output by the second memory controller of the first semiconductor chip and to input the selected control signal to the second memory interface of the first semiconductor chip. 
     
     
         25 . The electronic device according to  claim 23 , wherein the first semiconductor chip further comprises a mode terminal for setting the operation mode. 
     
     
         26 . The electronic device according to  claim 25 , wherein the first semiconductor chip further comprises a decoder configured to decode a value which is set to the mode terminal. 
     
     
         27 . The electronic device according to  claim 24 , wherein when the operation mode is a mode in which the first semiconductor chip communicates with the second semiconductor chip, the first selector selects the inter-device interface of the first semiconductor chip, and the second selector selects the first control signal. 
     
     
         28 . The electronic device according to  claim 23 , further comprising a plurality of monitors coupled to the first semiconductor chip and a plurality of monitors coupled to the second semiconductor chip. 
     
     
         29 . The electronic device according to  claim 28 , wherein the electronic device is a car navigation system. 
     
     
         30 . A semiconductor device comprising:
 a first and a second semiconductor chip, each of the first and second semiconductor chips being configured to be coupled to respective first and second external memories, and each of the first and second semiconductor chips including:   (a) a first memory interface configured to be coupled to a corresponding first external memory;   (b) a second memory interface configured to be coupled to a corresponding second external memory;   (c) a first memory controller coupled to the first memory interface such that a first control signal sent from the first memory controller passes through the first memory interface before reaching the first and second external memories;   (d) a second memory controller coupled to the second memory interface such that a second control signal sent from the second memory controller passes through the second memory interface before reaching the second external memory;   (e) an inter-device interface being configured to establish communication between the first semiconductor chip and the second semiconductor chip;   (f) terminals configured to output the second control signal that has passed through the second memory interface; and   (g) a first selector having an end connected only to the terminals and another end configured to be selectively connected to one of the second memory interface and the inter-device interface so as to select between connecting the second memory interface to the terminals and connecting the inter-device interface to the terminals in accordance with an operation mode of the semiconductor device,   wherein the first semiconductor chip is configured to access, through the inter-device interfaces of the first and second semiconductor chips, at least one of the first and second external memories coupled to the second semiconductor chip.   
     
     
         31 . The semiconductor device according to  claim 30 , wherein the first semiconductor chip further comprises a second selector different from the first selector and having an end connected only to the second memory interface and another end configured to be selectively connected to one of the first and second memory controllers so as to select between connecting the second memory interface to the first memory controller and connecting the second memory interface to the second memory controller. 
     
     
         32 . The semiconductor device according to  claim 31 , wherein the operation mode includes a first mode in which the first semiconductor chip communicates with the second semiconductor chip, and a second mode in which the first semiconductor chip is used singly. 
     
     
         33 . The semiconductor device according to  claim 32 , wherein in the first mode, the first selector of the first semiconductor chip selects and couples the inter-device interface of the first semiconductor chip to the terminals and the second selector selects the first control signal, and in the second mode, the first selector of the first semiconductor chip selects and couples the second memory interface of the first semiconductor chip to the terminals and the second selector selects the second control signal.