Power mosfet, an igbt, and a power diode

Abstract

Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.

1 .- 18 . (canceled) 
     
     
         19 . A semiconductor device comprising:
 a semiconductor substrate having a first main surface and a second main surface opposite each other,   a vertical power transistor;   a field plate of a ringed shape disposed over the first main surface and surrounding the vertical power transistor in the plan view, the field plate comprising:
 a first straight portion; 
 a second straight portion opposite to the first straight portion; 
 a third straight portion; and 
 a fourth straight portion opposite to the third straight portion, 
   first, second, third and fourth contact wirings extending along the first, second, third and fourth straight portions respectively, and each coupling the field plate with the first main surface;   wherein the first, second, third and fourth contact wirings are separated from each other.   
     
     
         20 . The semiconductor device according to  claim 19 ,
 wherein each of the first, second, third and fourth contact wirings has a length in the extending direction which is greater than each separation distance.   
     
     
         21 . The semiconductor device according to  claim 20 ,
 wherein the field plate further comprises:
 a first corner potion connecting the first straight portion and the third straight portion; 
 a second corner portion connecting the second straight portion and the third straight portion; 
 a third corner portion connecting the second straight portion and the fourth straight portion; and 
 the fourth corner portion connecting the first straight portion and the fourth straight portion, 
   wherein the first contact wiring and the third contact wiring are separated at the first corner portion in a plan view,   wherein the second contact wiring and the third contact wiring are separated at the second corner portion in the plan view,   wherein the second contact wiring and the fourth contact wiring are separated at the third corner portion in the plan view, and   wherein the first contact wiring and the fourth contact wiring are separated at the fourth corner portion in the plan view.   
     
     
         22 . The semiconductor device according to  claim 19 ,
 wherein the vertical power transistor comprises:   a gate electrode disposed over the first main surface;   a source electrode disposed over the first main surface; and   a drain electrode disposed over the second main surface.   
     
     
         23 . The semiconductor device according to  claim 22 ,
 wherein the field plate surrounds the source electrode in a plan view.   
     
     
         24 . A semiconductor device comprising:
 a semiconductor substrate having a first main surface and a second main surface opposite each other,   a vertical power transistor;   a field plate of a ringed shape disposed over the first main surface and surrounding the vertical power transistor in the plan view, the field plate comprising:
 a first straight portion; 
 a second straight portion opposite to the first straight portion; 
 a third straight portion; and 
 a fourth straight portion opposite to the third straight portion, 
   first, second, third and fourth contact wiring patterns extending along the first, second, third and fourth straight portions respectively, and each coupling the field plate with the first main surface;   wherein each of the first, second, third and fourth contact wiring patterns comprises a plurality of contact wirings arranged at a first interval.   
     
     
         25 . The semiconductor device according to  claim 24 ,
 wherein the first, second, third and fourth contact wiring patterns are separated by a separation distance from each other,   wherein the separation distance is greater than the first interval.   
     
     
         26 . The semiconductor device according to  claim 25 ,
 wherein the field plate further comprises:
 a first corner potion connecting the first straight portion and the third straight portion; 
 a second corner portion connecting the second straight portion and the third straight portion; 
 a third corner portion connecting the second straight portion and the fourth straight portion; and 
 the fourth corner portion connecting the first straight portion and the fourth straight portion, 
   wherein the first contact wiring pattern and the third contact wiring pattern are separated at the first corner portion in a plan view,   wherein the second contact wiring pattern and the third contact wiring pattern are separated at the second corner portion in the plan view,   wherein the second contact wiring pattern and the fourth contact wiring pattern are separated at the third corner portion in the plan view, and   wherein the first contact wiring pattern and the fourth contact wiring pattern are separated at the fourth corner portion in the plan view.   
     
     
         27 . The semiconductor device according to  claim 24 ,
 wherein the vertical power transistor comprises:   a gate electrode disposed over the first main surface;   a source electrode disposed over the first main surface; and   a drain electrode disposed over the second main surface.   
     
     
         28 . The semiconductor device according to  claim 27 ,
 wherein the field plate surrounds the source electrode in a plan view.